Converts every input clock into a clock enable input and adds a single global clock.
Converts every input clock into a clock enable input and adds a single global clock.
- all registers and memory ports will be connected to the new global clock
- all registers and memory ports will be guarded by the enable signal of their original clock
- the clock enabled signal can be understood as a clock tick or posedge
- this transform can be used in order to (formally) verify designs with multiple clocks or asynchronous resets
Converts every input clock into a clock enable input and adds a single global clock. - all registers and memory ports will be connected to the new global clock - all registers and memory ports will be guarded by the enable signal of their original clock - the clock enabled signal can be understood as a clock tick or posedge - this transform can be used in order to (formally) verify designs with multiple clocks or asynchronous resets