LegalizeClocksTransform

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1. final def !=(arg0: Any): Boolean

   

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2. final def ##(): Int

   

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3. final def ==(arg0: Any): Boolean

   

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4. final def asInstanceOf[T0]: T0

   

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5. def clone(): AnyRef

   

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6. final def eq(arg0: AnyRef): Boolean

   

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7. def equals(arg0: Any): Boolean

   

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8. def finalize(): Unit

   

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9. final def getClass(): Class[_]

   

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10. def hashCode(): Int

    

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11. final def isInstanceOf[T0]: Boolean

    

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12. final def ne(arg0: AnyRef): Boolean

    

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13. final def notify(): Unit

    

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14. final def notifyAll(): Unit

    

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15. def onMod(mod: DefModule): DefModule

    

16. def onStmt(namespace: ⇒ Namespace)(stmt: Statement): Statement

    

    Legalize Clocks in a Statement

    Legalize Clocks in a Statement

    Enforces legal Verilog semantics on all Clock Expressions. Legal is defined as what standard lint tools accept. Currently only Literal Expressions (guarded by casts) are handled.

    Note

    namespace is lazy because it should not typically be needed

17. final def synchronized[T0](arg0: ⇒ T0): T0

    

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18. def toString(): String

    

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19. final def wait(): Unit

    

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20. final def wait(arg0: Long, arg1: Int): Unit

    

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21. final def wait(arg0: Long): Unit

    

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