formal

class AssertSubmoduleAssumptions extends Transform with RegisteredTransform with DependencyAPIMigration with PreservesAll[Transform]

Assert Submodule Assumptions
Assert Submodule Assumptions
Converts assume statements to assert statements in all modules except the top module being compiled. This avoids a class of bugs in which an overly restrictive assume in a child module can prevent the model checker from searching valid inputs and states in the parent module.
class RemoveVerificationStatements extends Transform with DependencyAPIMigration with PreservesAll[Transform]

Remove Verification Statements
Remove Verification Statements
Replaces all verification statements in all modules with the empty statement. This is intended to be required by the Verilog emitter to ensure compatibility with the Verilog 2001 standard.

object AssertSubmoduleAssumptionsAnnotation extends NoTargetAnnotation with Product with Serializable
object ConvertAsserts extends Transform with DependencyAPIMigration

Convert Asserts
Convert Asserts
Replaces all Assert nodes with a gated print-and-stop. This effectively emulates the assert for IEEE 1364 Verilog.
object DontAssertSubmoduleAssumptionsAnnotation extends NoTargetAnnotation with Product with Serializable