MAX
PrimOps
MIN
PrimOps
MINUS
PrimOps
MInfer
firrtl
MPort
passes
MPortDir
firrtl
MPortDirMap
CInferMDir
MPortMap
RemoveCHIRRTL
MPortTypeMap
RemoveCHIRRTL
MPorts
passes
MRead
firrtl
MReadWrite
firrtl
MSet
GroupComponents
MWrite
firrtl
ManipulateNames
transforms
ManipulateNamesAllowlistAnnotation
transforms
ManipulateNamesAllowlistResultAnnotation
transforms
ManipulateNamesBlocklistAnnotation
transforms
ManipulateNamesListAnnotation
transforms
Mappers
firrtl
MaskedReadWritePort
memlib
MaskedWritePort
memlib
MaxCatLenAnnotation
transforms
MaxWidth
CheckWidths
MemConf
memlib
MemDelayAndReadwriteTransformer
memlib
MemKind
firrtl
MemLibOptions
memlib
MemPort
memlib
MemPortMap
MemPortUtils
MemPortUtils
passes
MemTransformUtils
memlib
MemWithFlipException
CheckHighFormLike
MemoizedHash
firrtl
Memories
MemPortUtils
MemoryArrayInit
firrtl
MemoryArrayInitAnnotation
annotations
MemoryEmissionOption
firrtl
MemoryEmissionOptionDefault
firrtl
MemoryInitAnnotation
annotations
MemoryInitValue
firrtl
MemoryLoadFileType
annotations
MemoryRandomInit
firrtl
MemoryRandomInitAnnotation
annotations
MemoryScalarInit
firrtl
MemoryScalarInitAnnotation
annotations
MidEmitters
Forms
MidForm
firrtl Forms
MiddleFirrtlCompiler
firrtl
MiddleFirrtlEmitter
firrtl
MiddleFirrtlToLowFirrtl
firrtl
MinimalHighForm
Forms
MinimumLowFirrtlOptimization
firrtl
MinimumVerilogCompiler
firrtl
MinimumVerilogEmitter
firrtl
Modifications
wiring
Module
ir
ModuleForeach
Foreachers
ModuleGraph
firrtl
ModuleHasInstanceOfModuleMap
DuplicationHelper
ModuleMap
Mappers
ModuleName
annotations
ModuleNameNotUniqueException
CheckHighFormLike
ModuleNameSerializer
JsonProtocol
ModuleNamespaceAnnotation
analyses
ModuleNotDefinedException
CheckHighFormLike
ModuleTarget
annotations
ModuleTargetSerializer
JsonProtocol
Modules
MemPortUtils
Mul
PrimOps
MulDoPrimGen
ExprGen
MultiAry
constraint
MultiBitAsAsyncReset
CheckWidths
MultiBitAsClock
CheckWidths
MultiInfo
ir
MultiTargetAnnotation
annotations
MutableConnMap
CheckCombLoops
MutableDiGraph
graph
MutableEdgeData
graph
Mux
ir
MuxClock
CheckTypes
MuxCondUInt
CheckTypes
MuxGen
ExprGen
MuxPassiveTypes
CheckTypes
MuxSameType
CheckTypes
main
Driver Circuit JQFFuzz JQFRepro StageMain
makeAbsolute
CircuitGraph
makeDirectory
FileUtils
makeHarness
BackendCompilationUtilities
makePathless
DuplicationHelper
makeScope
Logger
makeTargetDir
ExecutionOptionsManager
manager
PassBenchmark TransformBenchmark
manipulate
LetterCaseTransform ManipulateNames RemoveKeywordCollisions
map
CircuitMap ExprMap ModuleMap PortMap StmtMap TypeMap WidthMap Constraint IsAdd IsFloor IsKnown IsMax IsMin IsMul IsNeg IsPow IsVar GenMonad GenMonadOps SourceOfRandomnessGen StateGen CalcBound UnknownBound Lineage
mapExpr
CDefMPort CDefMemory EmptyExpression VRandom WDefInstanceConnector WInvalid WVoid Attach Block Conditionally Connect DefInstance DefMemory DefNode DefRegister DefWire DoPrim EmptyStmt Expression FixedLiteral IsInvalid Mux PartialConnect Print Reference SIntLiteral Statement Stop SubAccess SubField SubIndex UIntLiteral ValidIf Verification DefAnnotatedMemory
mapInfo
CDefMPort CDefMemory WDefInstanceConnector Attach Block Circuit Conditionally Connect DefInstance DefMemory DefModule DefNode DefRegister DefWire EmptyStmt ExtModule IsInvalid Module PartialConnect Print Statement Stop Verification DefAnnotatedMemory
mapModule
Circuit
mapPort
DefModule ExtModule Module
mapStmt
CDefMPort CDefMemory WDefInstanceConnector Attach Block Conditionally Connect DefInstance DefMemory DefModule DefNode DefRegister DefWire EmptyStmt ExtModule IsInvalid Module PartialConnect Print Statement Stop Verification DefAnnotatedMemory
mapString
CDefMPort CDefMemory WDefInstanceConnector Attach Block Circuit Conditionally Connect DefInstance DefMemory DefModule DefNode DefRegister DefWire EmptyStmt ExtModule IsInvalid Module PartialConnect Port Print Statement Stop Verification DefAnnotatedMemory
mapType
CDefMPort CDefMemory EmptyExpression VRandom WDefInstanceConnector WInvalid WVoid Attach Block BundleType Conditionally Connect DefInstance DefMemory DefNode DefRegister DefWire DoPrim EmptyStmt Expression FixedLiteral GroundType IsInvalid Mux PartialConnect Port Print Reference SIntLiteral Statement Stop SubAccess SubField SubIndex Type UIntLiteral UnknownType ValidIf VectorType Verification DefAnnotatedMemory
mapWidth
EmptyExpression VRandom WInvalid WVoid AggregateType AnalogType AsyncResetType ClockType DoPrim Expression FixedLiteral FixedType IntervalType Mux Reference ResetType SIntLiteral SIntType SubAccess SubField SubIndex Type UIntLiteral UIntType UnknownType ValidIf
mask
DataRef
maskBigInt
Utils
maskBits
ReplaceMemMacros
maskGran
DefAnnotatedMemory
maskGranularity
MemConf
masked
UIntLiteral
matchingArgsValue
FoldADD FoldAND FoldEqual FoldNotEqual FoldOR FoldXOR SimplifyBinaryOp SimplifyDIV SimplifyREM SimplifySUB
max
Utils IsKnown Closed IntervalType Open Width InlineBooleanExpressionsMax
maxAdjusted
IntervalType
maxCatLen
MaxCatLenAnnotation
maxDepth
ExprGenParams
maxMemSize
VerilogRender
maxWidth
ExprGenParams ExprState
maxs
IsAdd IsMin
mdir
FIRRTLParser
mem
CDefMPort
memField
FIRRTLParser
memPortField
MemPortUtils MemTransformUtils
memRef
DefAnnotatedMemory
memToBundle
ReplaceMemMacros
memToFlattenBundle
ReplaceMemMacros
memType
MemPortUtils
memlib
passes
memoryInitials
VerilogRender
memport
LogicNode
merge
MultiAry
mergeDescriptions
AddDescriptionNodes
mergeRef
Utils
mergeTransforms
CompilerUtils
message
OptionsException EmitterException FirrtlExecutionFailure InvalidEscapeCharException InvalidStringLitException ParameterNotSpecifiedException ParameterRedefinedException SyntaxErrorsException AnnotationException NamedException NoSuchTargetException JQFException DependencyManagerException OptionsException PhaseException TreeCleanUpOrphanException
migrationDocumentLink
CheckScalaVersion
min
Utils IsKnown Closed IntervalType Open Width
minAdjusted
IntervalType
minNegValue
FixAddingNegativeLiterals
minWidth
SIntLiteral UIntLiteral
mins
IsAdd IsMax
modeName
InfoModeAnnotation
modify
Target
module
WDefInstanceConnector InstanceKey CircuitTarget ComponentName InstanceTarget IsMember ModuleTarget ReferenceTarget FIRRTLParser DefInstance Source
moduleBlock
FIRRTLParser
moduleLeafPortTargets
IRLookup
moduleMap
InstanceGraph InstanceKeyGraph
moduleOpt
CircuitTarget GenericTarget InstanceTarget ModuleTarget ReferenceTarget Target
moduleOrder
InstanceGraph InstanceKeyGraph
moduleTarget
VerilogRender IsMember
module_type
Utils
modules
InstanceGraph Circuit
msg
DeclarationNotFoundException InvalidAnnotationJSONException Verification WiringException
mux_type
Utils
mux_type_and_widths
Utils