Declaration kind in lineage (e.g.
Declaration kind in lineage (e.g. input port, output port, wire)
Store of pending wiring information for a Module
A module, e.g.
A module, e.g. ExtModule etc., that should add the input pin
A component, e.g.
A component, e.g. register etc. Must be declared only once under the TopAnnotation
Pass that computes and applies a sequence of wiring modifications
A class for all exceptions originating from firrtl.passes.wiring
A data store of one sink--source wiring relationship
A data store of wiring names
Wires a Module's Source Target to one or more Sink Modules/Components
Wires a Module's Source Target to one or more Sink Modules/Components
Sinks are wired to their closest source through their lowest common ancestor (LCA). Verbosely, this modifies the circuit in the following ways:
WiringException
if a sink is equidistant to two sources
A lineage tree representing the instance hierarchy in a design
A lineage tree representing the instance hierarchy in a design
(Since version 1.1.1) Use DiGraph/InstanceGraph