RawStringParam
ir
ReadPort
memlib
ReadUnderWrite
ir
ReadWritePort
memlib
ReductionDoPrimGen
ExprGen
Ref
TargetToken
fromStringToTargetToken
RefLikeExpression
ir
RefNotInitializedException
CheckInitialization
Reference
ir
ReferenceGen
ExprGen
ReferenceTarget
annotations
ReferenceTargetSerializer
JsonProtocol
RegKind
firrtl
RegReqClk
CheckTypes
RegWithFlipException
CheckHighFormLike
RegisterEmissionOption
firrtl
RegisterEmissionOptionDefault
firrtl
RegisteredLibrary
options
RegisteredTransform
options
Rem
PrimOps
RemDoPrimGen
ExprGen
RemoveAccesses
passes
RemoveAllButClocks
clocklist
RemoveCHIRRTL
passes
RemoveEmpty
passes
RemoveIntervals
passes
RemoveKeywordCollisions
transforms
RemoveReset
transforms
RemoveValidIf
passes
RemoveVerificationStatements
formal
RemoveWires
transforms
RenameAnnotatedMemoryPorts
memlib
RenameMap
firrtl
RenameModules
transforms
RenameTargetException
RenameMap
RenderDiGraph
graph
ReplSeqMem
memlib
ReplSeqMemAnnotation
memlib
ReplaceAccesses
passes
ReplaceMemMacros
memlib
ReplaceTruncatingArithmetic
transforms
ReqClk
CheckTypes
Reset
TargetToken
ResetExtModuleOutputException
CheckHighFormLike
ResetInputException
CheckHighFormLike
ResetType
ir
ResolveAndCheck
firrtl
ResolveFlows
passes
ResolveKinds
passes
ResolveKindsBenchmark
hot
ResolveMaskGranularity
memlib
ResolveMemoryReference
memlib
ResolvePaths
transforms
Resolved
Forms
ResolvedAnnotationPaths
firrtl
RunFirrtlTransformAnnotation
stage
rand_string
VerilogRender
range
IntervalType
rdwrite
DataRef
reachableFrom
DiGraph
reachableModules
InstanceGraph
InstanceKeyGraph
readLatency
DefMemory
DefAnnotatedMemory
readUnderWrite
CDefMemory
DefMemory
DefAnnotatedMemory
readers
DefMemory
MPorts
DefAnnotatedMemory
readwriters
DefMemory
MPorts
DefAnnotatedMemory
realWidth
VRandom
reason
CircularRenameException
IllegalRenameException
record
RenameMap
recordAll
RenameMap
reduce
Constraint
IsAdd
IsFloor
IsKnown
IsMax
IsMin
IsMul
IsNeg
IsPow
IsVar
CalcBound
UnknownBound
FoldANDR
FoldORR
FoldXORR
SimplifyReductionOp
ref
InstanceTarget
IsModule
ModuleTarget
ReferenceTarget
referringModule
Target
regUpdate
VerilogRender
regex
MemConf
registeredLibraries
Shell
registeredTransforms
Shell
remove
GenericTarget
removeVerification
RemoveVerificationStatements
remove_chirrtl_m
RemoveCHIRRTL
remove_chirrtl_s
RemoveCHIRRTL
remove_root
VerilogEmitter
rename
RenameMap
renameModules
EliminateTargetPaths
renames
CircuitState
renderNode
RenderDiGraph
reorderModules
EliminateTargetPaths
replaceExp
InferReadWritePass
replaceStmt
InferReadWritePass
replacements
EmittedFirrtlCircuitAnnotation
CustomFileEmission
reportError
ExceptOnError
reset
ReferenceTarget
DefRegister
Logger
reset_block
FIRRTLParser
resolvePaths
CircuitState
resolvePathsOf
CircuitState
resolve_e
ResolveFlows
resolve_expr
ResolveKinds
resolve_flow
ResolveFlows
resolve_kinds
ResolveKinds
resolve_s
ResolveFlows
resolve_stmt
ResolveKinds
resourceFileName
BlackBoxResourceFileNameAnno
resourceId
BlackBoxResourceAnno
ret
Stop
reverse
DiGraph
reverseConnectionGraph
ConnectionGraph
right
GreaterOrEqual
Inequality
LesserOrEqual
rmq
EulerTour
rmqBV
EulerTour
rmqNaive
EulerTour
run
EliminateTargetPaths
StateGen
Stage
CInferMDir
CInferTypes
CheckFlows
CheckHighFormLike
CheckInitialization
CheckTypes
CheckWidths
CommonSubexpressionElimination
ConvertFixedToSInt
ExpandConnects
ExpandWhens
InferBinaryPoints
InferTypes
InferWidths
InlineInstances
Legalize
PadWidths
Pass
PullMuxes
RemoveAccesses
RemoveEmpty
RemoveIntervals
RemoveValidIf
ReplaceAccesses
ResolveFlows
ResolveKinds
SplitExpressions
ToWorkingIR
TrimIntervals
VerilogModulusCleanup
VerilogPrep
ZeroLengthVecs
ClockList
RemoveAllButClocks
InferReadWritePass
RenameAnnotatedMemoryPorts
ResolveMaskGranularity
ResolveMemoryReference
ToMemIR
VerilogMemDelays
Wiring
FirrtlStage
DeadCodeElimination
DedupModules
ManipulateNames
AssertSubmoduleAssumptions
RemoveVerificationStatements
runTimeout
JQFFuzzOptions
runTransform
Transform
runTransforms
SeqTransformBased
runs
PassBenchmark
SerializationBenchmark
TransformBenchmark
ruw
FIRRTLParser