CDefMPort
firrtl
CDefMemory
firrtl
CInferMDir
passes
CInferTypes
passes
CalcBound
ir
CalcWidth
ir
Cat
PrimOps
CatDoPrimGen
ExprGen
CatchCustomTransformExceptions
transforms
CatchExceptions
phases
CharMap
FileInfo
CharSet
DependencyManagerUtils
CheckChirrtl
passes
CheckCombLoops
transforms
CheckFlows
passes
CheckHighForm
passes
CheckHighFormBenchmark
hot
CheckHighFormLike
passes
CheckInitialization
passes
CheckResets
checks
CheckScalaVersion
transforms
CheckTypes
passes
CheckWidths
passes
CheckWidthsBenchmark
hot
Checks
phases Forms phases phases
ChildrenMap
WiringUtils
ChirrtlEmitter
firrtl
ChirrtlEmitters
Forms
ChirrtlForm
firrtl Forms
ChirrtlToHighFirrtl
firrtl
Circuit
ir
CircuitForeach
Foreachers
CircuitForm
firrtl
CircuitGraph
analyses
CircuitMap
Mappers
CircuitName
annotations
CircuitNameSerializer
JsonProtocol
CircuitOption
stage
CircuitSerializer
JsonProtocol
CircuitState
firrtl
CircuitTarget
annotations
CircuitTargetSerializer
JsonProtocol
CircularRenameException
RenameMap
ClassLogLevelAnnotation
logger
ClassUtils
util
CleanupNamedTargets
transforms
Clip
PrimOps
Clock
TargetToken
ClockList
clocklist
ClockListAnnotation
clocklist
ClockListTransform
clocklist
ClockListUtils
clocklist
ClockType
ir
ClockZero
RemoveValidIf
Closed
ir
CmpDoPrimGen
ExprGen
CombLoopException
CheckCombLoops
CombinationalPath
transforms
CombineCats
transforms
CommonOptions
firrtl
CommonSubexpressionElimination
passes
Compiler
firrtl phases transforms
CompilerAnnotation
stage
CompilerUtils
firrtl
CompleteTarget
annotations
CompleteTargetSerializer
JsonProtocol
ComponentName
annotations
ComponentNameSerializer
JsonProtocol
ComposableOptions
firrtl
Conditionally
ir
ConfWriter
memlib
Config
memlib
ConnMap
CheckCombLoops
Connect
ir
ConnectEmissionOption
firrtl
ConnectEmissionOptionDefault
firrtl
ConnectionGraph
analyses
Connects
AnalysisUtils
ConstantPropagation
transforms
Constraint
constraint
ConstraintMap
ConstraintSolver
ConstraintSolver
constraint
ConvertAsserts
formal
ConvertFixedToSInt
passes
ConvertLegacyAnnotations
phases
CoreTransform
firrtl
Cover
Formal
CreateMemoryAnnotations
memlib
CustomFileEmission
options
CustomTransformException
firrtl
CustomYAMLProtocol
memlib
Cvt
PrimOps
CvtDoPrimGen
ExprGen
CyclicException
graph
c1
PrimOps
c2
PrimOps
calcPoint
ConvertFixedToSInt
canEqual
IntWidth
candidates
DedupFailure
castRhs
firrtl
cause
CustomTransformException InvalidAnnotationFileException TraceException DependencyManagerException
chained
RenameMap
changeInternals
DedupModules
check
ConstraintSolver InlineInstances
checkComplement
InferReadWritePass
checks
firrtl
child
IsFloor IsNeg IsPow
children
Constraint IsAdd IsFloor IsKnown IsMax IsMin IsMul IsNeg IsPow IsVar CalcBound UnknownBound Lineage
choose
GenMonad
circuit
CircuitState ConnectionGraph CircuitTarget CompleteTarget InstanceTarget ModuleName ModuleTarget ReferenceTarget FIRRTLParser FirrtlCircuitAnnotation
circuitOpt
CircuitTarget GenericTarget InstanceTarget ModuleTarget ReferenceTarget Target
circuitState
FirrtlExecutionSuccess
circuitTarget
CompleteTarget
classLogLevels
CommonOptions LoggerOptions
className
AnnotationClassNotFoundException ClassLogLevelAnnotation
classpath
JQFFuzzOptions JQFReproOptions
clear
ConstraintSolver OutputCaptor
clearStringBuffer
Logger
clk
Print Stop Verification MPort
clock
ReferenceTarget DefRegister
clocklist
passes
cloneUnderlying
Namespace
code
StageError
collectAnnos
BlackBoxSourceHelper
collectInstances
InstanceGraph InstanceKeyGraph
collectMaps
AddDescriptionNodes
collectNameMapping
RenameModules
collect_refs
RemoveCHIRRTL
collect_smems_and_mports
RemoveCHIRRTL
colormap
DependencyManager
commonOptions
HasCommonOptions
compName
WiringNames
compare
CircuitForm UnknownForm
compile
Compiler FirrtlCompileTests
compileAndEmit
Compiler
compileSingleModule
FirrtlCompileTests
compiler
FirrtlExecutionOptions CompilerAnnotation
compilerName
FirrtlExecutionOptions
complete
Target
component
ReferenceTarget
componentType
ReferenceTarget
components
GroupAnnotation
computeIndexedNames
DedupModules
computeRenameMap
DedupModules
cond
Mux ValidIf
condConnect
MemDelayAndReadwriteTransformer
connect
MemDelayAndReadwriteTransformer
connectFields
firrtl
connectionPath
CircuitGraph
conns
SplitStatements
cons
Lineage Modifications
conseq
Conditionally
const
GenMonad
constPropBitExtract
ConstantPropagation
constraint
firrtl
constraint2bound
Implicits
constraint2width
Implicits
constructNameMap
ReplaceMemMacros
consts
DoPrim
contains
Namespace IRLookup DiGraph
continuation
ASCIICharSet CharSet PrettyCharSet
convert
FromProto ToProto
convertAsserts
ConvertAsserts
convertCircuitName2CircuitTarget
Target
convertCircuitTarget2CircuitName
Target
convertComponentName2ReferenceTarget
Target
convertFrom
MemoizedHash
convertIsComponent2ComponentName
Target
convertModuleName2ModuleTarget
Target
convertModuleTarget2ModuleName
Target
convertNamed2Target
Target
convertTarget2Named
Target
convertTo
MemoizedHash
convertToBigInt
ToProto
convertToIntegerLiteral
ToProto
copy
RenameMap IntWidth DependencyManager PhaseManager TransformManager
copyResourceToFile
BlackBoxSourceHelper BackendCompilationUtilities
coverageClasses
TestOptions
cppToExe
BackendCompilationUtilities
create
RenameMap
createMask
passes
createMemModule
ReplaceMemMacros
createMemProto
RenameAnnotatedMemoryPorts
createTestDirectory
BackendCompilationUtilities
create_all_exps
RemoveCHIRRTL
create_exps
Utils RemoveCHIRRTL
currentModule
GroupAnnotation
currentState
DependencyManager PhaseManager TransformManager
customPrintHandling
DependencyManager Compiler
customTransforms
FirrtlExecutionOptions