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firrtl.util

BackendCompilationUtilities

trait BackendCompilationUtilities extends LazyLogging

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  1. final def !=(arg0: Any): Boolean
    Definition Classes
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  2. final def ##(): Int
    Definition Classes
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  3. final def ==(arg0: Any): Boolean
    Definition Classes
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  4. lazy val TestDirectory: File

    Parent directory for tests

  5. final def asInstanceOf[T0]: T0
    Definition Classes
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  6. def clone(): AnyRef
    Attributes
    protected[lang]
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    @throws( ... ) @native()
  7. def copyResourceToFile(name: String, file: File): Unit

    Copy the contents of a resource to a destination file.

    Copy the contents of a resource to a destination file.

    name

    the name of the resource

    file

    the file to write it into

  8. def cppToExe(prefix: String, dir: File): ProcessBuilder
  9. def createTestDirectory(testName: String): File

    Create a test directory

    Create a test directory

    Will create outer directory called testName then inner directory based on the current time

  10. final def eq(arg0: AnyRef): Boolean
    Definition Classes
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  11. def equals(arg0: Any): Boolean
    Definition Classes
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  12. def executeExpectingFailure(prefix: String, dir: File, assertionMsg: String = ""): Boolean
  13. def executeExpectingSuccess(prefix: String, dir: File): Boolean
  14. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
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    @throws( classOf[java.lang.Throwable] )
  15. def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder

    compule chirrtl to verilog by using a separate process

    compule chirrtl to verilog by using a separate process

    prefix

    basename of the file

    dir

    directory where file lives

    returns

    true if compiler completed successfully

  16. final def getClass(): Class[_]
    Definition Classes
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    @native()
  17. def hashCode(): Int
    Definition Classes
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    @native()
  18. final def isInstanceOf[T0]: Boolean
    Definition Classes
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  19. val logger: Logger
    Attributes
    protected
    Definition Classes
    LazyLogging
  20. def loggingProcessLogger: ProcessLogger
  21. def makeHarness(template: (String) ⇒ String, post: String)(f: File): File
  22. final def ne(arg0: AnyRef): Boolean
    Definition Classes
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  23. final def notify(): Unit
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    @native()
  24. final def notifyAll(): Unit
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    @native()
  25. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
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  26. def timeStamp: String
  27. def toString(): String
    Definition Classes
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  28. def verilogToCpp(dutFile: String, dir: File, vSources: Seq[File], cppHarness: File, suppressVcd: Boolean = false, resourceFileName: String = ...): ProcessBuilder

    Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.

    Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.

    The Verilator prefix will be V$dutFile, and running this will generate C++ sources and headers as well as a makefile to compile them.

    Verilator will automatically locate the top-level module as the one among all the files which are not included elsewhere. If multiple ones exist, the compilation will fail.

    If the file BlackBoxSourceHelper.fileListName (or an overridden .f resource filename that is specified with the optional resourceFileName parameter) exists in the output directory, it contains a list of source files to be included. Filter out any files in the vSources sequence that are in this file so we don't include the same file multiple times. This complication is an attempt to work-around the fact that clients used to have to explicitly include additional Verilog sources. Now, more of that is automatic.

    dutFile

    name of the DUT .v without the .v extension

    dir

    output directory

    vSources

    list of additional Verilog sources to compile

    cppHarness

    C++ testharness to compile/link against

    suppressVcd

    specifies if VCD tracing should be suppressed

    resourceFileName

    specifies what filename to look for to find a .f file

  29. final def wait(): Unit
    Definition Classes
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    Annotations
    @throws( ... )
  30. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
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    @throws( ... )
  31. final def wait(arg0: Long): Unit
    Definition Classes
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    @throws( ... ) @native()
  32. def yosysExpectFailure(customTop: String, referenceTop: String, testDir: File, resets: Seq[(Int, String, Int)] = Seq.empty): Boolean

    Creates and runs a Yosys script that creates and runs SAT on a miter circuit.

    Creates and runs a Yosys script that creates and runs SAT on a miter circuit. Returns false if SAT succeeds, true otherwise

    The custom and reference Verilog files must not contain any modules with the same name otherwise Yosys will not be able to create a miter circuit

    customTop

    name of the DUT with custom transforms without the .v extension

    referenceTop

    name of the DUT without custom transforms without the .v extension

    testDir

    directory containing verilog files

    resets

    signals to set for SAT, format is (timestep, signal, value)

  33. def yosysExpectSuccess(customTop: String, referenceTop: String, testDir: File, resets: Seq[(Int, String, Int)] = Seq.empty): Boolean

    Creates and runs a Yosys script that creates and runs SAT on a miter circuit.

    Creates and runs a Yosys script that creates and runs SAT on a miter circuit. Returns true if SAT succeeds, false otherwise

    The custom and reference Verilog files must not contain any modules with the same name otherwise Yosys will not be able to create a miter circuit

    customTop

    name of the DUT with custom transforms without the .v extension

    referenceTop

    name of the DUT without custom transforms without the .v extension

    testDir

    directory containing verilog files

    resets

    signals to set for SAT, format is (timestep, signal, value)

Inherited from LazyLogging

Inherited from AnyRef

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