sealed trait MemoryInitAnnotation extends SingleTargetAnnotation[ReferenceTarget] with MemoryEmissionOption
Represents the initial value of the annotated memory. While not supported on normal ASIC flows, it can be useful for simulation and FPGA flows. This annotation is consumed by the verilog emitter.
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abstract
def
canEqual(that: Any): Boolean
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abstract
def
duplicate(n: ReferenceTarget): Annotation
Create another instance of this Annotation
Create another instance of this Annotation
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- SingleTargetAnnotation
- abstract def isRandomInit: Boolean
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abstract
def
productArity: Int
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abstract
def
productElement(n: Int): Any
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abstract
val
target: ReferenceTarget
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: Any): Boolean
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final
def
asInstanceOf[T0]: T0
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def
clone(): AnyRef
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def
eq(arg0: AnyRef): Boolean
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def
equals(arg0: Any): Boolean
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def
finalize(): Unit
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final
def
getClass(): Class[_]
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def
getTargets: Seq[Target]
Returns all Target members in this annotation
Returns all Target members in this annotation
- Definition Classes
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def
hashCode(): Int
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def
initValue: MemoryInitValue
- Definition Classes
- MemoryEmissionOption
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final
def
isInstanceOf[T0]: Boolean
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final
def
ne(arg0: AnyRef): Boolean
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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def
productIterator: Iterator[Any]
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def
productPrefix: String
- Definition Classes
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def
serialize: String
Optional pretty print
Optional pretty print
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rarely used
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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def
update(renames: RenameMap): Seq[Annotation]
Update the target based on how signals are renamed
Update the target based on how signals are renamed
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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