package memlib
- Alphabetic
- Public
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Type Members
- case class Config(pin: Pin, source: Source, top: Top) extends Product with Serializable
- class CreateMemoryAnnotations extends Transform with DependencyAPIMigration
- case class DefAnnotatedMemory(info: Info, name: String, dataType: Type, depth: BigInt, writeLatency: Int, readLatency: Int, readers: Seq[String], writers: Seq[String], readwriters: Seq[String], readUnderWrite: ir.ReadUnderWrite.Value, maskGran: Option[BigInt], memRef: Option[(String, String)]) extends Statement with IsDeclaration with Product with Serializable
- sealed trait DefaultReadUnderWriteAnnotation extends NoTargetAnnotation
- class DumpMemoryAnnotations extends Transform with DependencyAPIMigration
- case class GenVerilogMemBehaviorModelAnno(genBlackBox: Boolean) extends NoTargetAnnotation with Product with Serializable
- class InferReadWrite extends Transform with DependencyAPIMigration with SeqTransformBased with HasShellOptions
- case class MemConf(name: String, depth: BigInt, width: Int, ports: Map[MemPort, Int], maskGranularity: Option[Int]) extends Product with Serializable
-
class
MemDelayAndReadwriteTransformer extends AnyRef
This class performs the primary work of the transform: splitting readwrite ports into separate read and write ports while simultaneously compiling memory latencies to combinational-read memories with delay pipelines.
This class performs the primary work of the transform: splitting readwrite ports into separate read and write ports while simultaneously compiling memory latencies to combinational-read memories with delay pipelines. It is represented as a class that takes a module as a constructor argument, as it encapsulates the mutable state required to analyze and transform one module.
- Note
The final transformed module is found in the (sole public) field transformed
- class MemLibOptions extends RegisteredLibrary
-
case class
MemLibOutConfigFileAnnotation(file: String, annotatedMemories: Seq[DefAnnotatedMemory]) extends NoTargetAnnotation with CustomFileEmission with Product with Serializable
Generate conf file for a sequence of DefAnnotatedMemory
Generate conf file for a sequence of DefAnnotatedMemory
- Note
file already has its suffix adding by
--replSeqMem
- sealed abstract class MemPort extends AnyRef
-
case class
NoDedupMemAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] with Product with Serializable
A component, e.g.
A component, e.g. register etc. Must be declared only once under the TopAnnotation
- sealed trait PassOption extends AnyRef
- case class Pin(name: String) extends Product with Serializable
-
case class
PinAnnotation(pins: Seq[String]) extends NoTargetAnnotation with Product with Serializable
Annotates the name of the pins to add for WiringTransform
- class ReplSeqMem extends SeqTransform with HasShellOptions with DependencyAPIMigration
- case class ReplSeqMemAnnotation(inputFileName: String, outputConfig: String) extends NoTargetAnnotation with Product with Serializable
-
class
ReplaceMemMacros extends Transform with DependencyAPIMigration
Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file.
Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file. This will not generate wmask ports if not needed. Creates the minimum # of black boxes needed by the design.
-
class
ResolveMemoryReference extends Transform with DependencyAPIMigration
Resolves annotation ref to memories that exactly match (except name) another memory
-
class
SeparateWriteClocks extends Transform with DependencyAPIMigration
This transform introduces an intermediate wire on the clock field of each write port of synchronous-read memories that have *multiple* write/readwrite ports and undefined read-under-write collision behavior.
This transform introduces an intermediate wire on the clock field of each write port of synchronous-read memories that have *multiple* write/readwrite ports and undefined read-under-write collision behavior. Ultimately, the introduction of these intermediate wires does not change which clock net clocks each port; therefore, the purpose of this transform is to help generate Verilog that is more amenable to inference of RAM macros with multiple write ports in FPGA synthesis flows. This change will cause each write and each readwrite port to be emitted in a separate clocked procedure, yielding multiple benefits:
1) Separate write procedures avoid implicitly constraining cross-port read-write and write-write collision behaviors 2) The preference for separate clocked procedures for each write port is explicitly specified by Intel and Xilinx
While this feature is not intended to be vendor-specific, inference of *multiple-write* RAM macros from behavioral Verilog or VHDL requires both advanced underlying RAM primitives and advanced synthesis tools. Currently, mapping such memories to programmable devices beyond modern Intel and Xilinx architectures can be prohibitive for users.
Though the emission of separate processes for write ports could be absorbed into the Verilog emitter, the use of a pure-FIRRTL transform reduces implementation complexity and enhances reliability.
-
class
SetDefaultReadUnderWrite extends Transform with DependencyAPIMigration
Adding a DefaultReadUnderWriteAnnotation and running the SetDefaultReadUnderWrite transform will cause all synchronous-read memories with 'undefined' read-under-write parameters to be assigned a default parameter value, either 'old' (read-first behavior) or 'new' (write-first behavior).
Adding a DefaultReadUnderWriteAnnotation and running the SetDefaultReadUnderWrite transform will cause all synchronous-read memories with 'undefined' read-under-write parameters to be assigned a default parameter value, either 'old' (read-first behavior) or 'new' (write-first behavior). This can help generate Verilog that is amenable to RAM macro inference for various FPGA tools, or it can be used to satisfy other downstream design constraints.
- class SimpleMidTransform extends SimpleTransform
- case class Source(name: String, module: String) extends Product with Serializable
- case class Top(name: String) extends Product with Serializable
- class YamlFileReader extends AnyRef
- class YamlFileWriter extends AnyRef
-
class
SimpleTransform extends Transform
- Annotations
- @deprecated
- Deprecated
(Since version FIRRTL 1.3) Migrate to a transform that does not take arguments. This will be removed in 1.4.
Value Members
- object AnalysisUtils
- object CustomYAMLProtocol extends DefaultYamlProtocol
- object DefAnnotatedMemory extends Serializable
-
object
DefaultReadFirstAnnotation extends DefaultReadUnderWriteAnnotation with Product with Serializable
This annotation directs the SetDefaultReadUnderWrite transform to assign a default value of 'old' (read-first behavior) to all synchronous-read memories with 'undefined' read-under-write parameters.
-
object
DefaultWriteFirstAnnotation extends DefaultReadUnderWriteAnnotation with Product with Serializable
This annotation directs the SetDefaultReadUnderWrite transform to assign a default value of 'new' (write-first behavior) to all synchronous-read memories with 'undefined' read-under-write parameters.
- object InferReadWriteAnnotation extends NoTargetAnnotation with Product with Serializable
- object InferReadWritePass extends Pass
- object InputConfigFileName extends PassOption with Product with Serializable
- object MaskedReadWritePort extends MemPort with Product with Serializable
- object MaskedWritePort extends MemPort with Product with Serializable
- object MemConf extends Serializable
- object MemDelayAndReadwriteTransformer
- object MemPort
- object MemTransformUtils
- object OutputConfigFileName extends PassOption with Product with Serializable
- object PassCircuitName extends PassOption with Product with Serializable
- object PassConfigUtil
- object PassModuleName extends PassOption with Product with Serializable
-
object
PassthroughSimpleSyncReadMemsAnnotation extends NoTargetAnnotation with Product with Serializable
Adding this annotation will allow the VerilogMemDelays transform to let 'simple' synchronous-read memories to pass through without explicitly breaking them apart into combinational-read memories and pipeline registers.
Adding this annotation will allow the VerilogMemDelays transform to let 'simple' synchronous-read memories to pass through without explicitly breaking them apart into combinational-read memories and pipeline registers. Here, 'simple' memories are defined as those that have one-cycle read and write latencies AND either no readwrite ports or read-under-write behavior that is either 'undefined' or 'old'. This second restriction avoids the particularly complex case of blending FIRRTL readwrite port semantics with cross-port 'bypassing' of new data on collisions.
- object ReadPort extends MemPort with Product with Serializable
- object ReadWritePort extends MemPort with Product with Serializable
-
object
RenameAnnotatedMemoryPorts extends Pass
Changes memory port names to standard port names (i.e.
Changes memory port names to standard port names (i.e. RW0 instead T_408)
- object ReplSeqMemAnnotation extends Serializable
- object ReplaceMemMacros
-
object
ResolveMaskGranularity extends Pass
Determines if a write mask is needed (wmode/en and wmask are equivalent).
Determines if a write mask is needed (wmode/en and wmask are equivalent). Populates the maskGran field of DefAnnotatedMemory Annotations:
- maskGran = (dataType size) / (number of mask bits)
- i.e. 1 if bitmask, 8 if bytemask, absent for no mask TODO(shunshou): Add floorplan info?
- maskGran = (dataType size) / (number of mask bits)
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object
ToMemIR extends Pass
Annotates sequential memories that are candidates for macro replacement.
Annotates sequential memories that are candidates for macro replacement. Requirements for macro replacement:
- read latency and write latency of one
- only one readwrite port or write port
- zero or one read port
- undefined read-under-write behavior
- object VerilogMemDelays extends Pass
- object WritePort extends MemPort with Product with Serializable
This is the documentation for Firrtl.