class VerilogRender extends AnyRef
Used by getRenderer, it has machinery to produce verilog from IR. Making this a class allows access to particular parts of the verilog emission.
- Source
- VerilogEmitter.scala
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- By Inheritance
- VerilogRender
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- Any
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- Public
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Instance Constructors
- new VerilogRender(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer)
- new VerilogRender(m: Module, moduleMap: Map[String, DefModule], circuitName: String, emissionOptions: EmissionOptions)(implicit writer: Writer)
-
new
VerilogRender(description: Seq[Description], portDescriptions: Map[String, Seq[Description]], m: Module, moduleMap: Map[String, DefModule], circuitName: String, emissionOptions: EmissionOptions)(implicit writer: Writer)
- description
a description of the start module
- portDescriptions
a map of port name to description
- m
the start module
- moduleMap
a map of modules so submodules can be discovered
- writer
where rendered information is placed.
Value Members
-
final
def
!=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
final
def
##(): Int
- Definition Classes
- AnyRef → Any
-
final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def addFormal(clk: Expression, en: Expression, stmt: Seq[Any], info: Info, msg: StringLit): Unit
-
final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
- def assign(e: Expression, value: Expression, info: Info): Unit
- def assign(e: Expression, infoExpr: InfoExpr): Unit
- val assigns: ArrayBuffer[Seq[Any]]
- val asyncInitials: ArrayBuffer[Seq[Any]]
- val asyncResetAlwaysBlocks: ArrayBuffer[(Expression, Expression, Seq[Any])]
- val attachAliases: ArrayBuffer[Seq[Any]]
- val attachSynAssigns: ArrayBuffer[Seq[Any]]
- def bigIntToVLit(bi: BigInt): String
- def build_attribute(attrs: String): Seq[Seq[String]]
- def build_comment(desc: String): Seq[Seq[String]]
- def build_description(d: Seq[Description]): Seq[Seq[String]]
- def build_netlist(s: Statement): Unit
- def build_ports(): Unit
- def build_streams(s: Statement): Unit
-
def
clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native() @HotSpotIntrinsicCandidate()
- def declare(b: String, n: String, t: Type, info: Info): Unit
- def declare(b: String, n: String, t: Type, info: Info, preset: Expression): Any
- def declareVectorType(b: String, n: String, tpe: Type, size: BigInt, info: Info, preset: Expression): Unit
- def declareVectorType(b: String, n: String, tpe: Type, size: BigInt, info: Info): Unit
- val declares: ArrayBuffer[Seq[Any]]
-
def
emitVerilogBind(overrideName: String, body: String): DefModule
This emits a verilog module that can be bound to a module defined in chisel.
This emits a verilog module that can be bound to a module defined in chisel. It uses the same machinery as the general emitter in order to insure that parameters signature is exactly the same as the module being bound to
- overrideName
Override the module name
- body
the body of the bind module
- returns
A module constructed from the body
- def emit_streams(): Unit
-
def
emit_verilog(): DefModule
The standard verilog emitter, wraps up everything into the verilog
-
final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
def
equals(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def formalStatement(op: ir.Formal.Value, cond: Expression): Seq[Any]
- val formals: LinkedHashMap[Expression, ArrayBuffer[Seq[Any]]]
- def garbageAssign(e: Expression, syn: Expression, garbageCond: Expression, info: Info): ArrayBuffer[Seq[Any]]
-
final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
def
hashCode(): Int
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- val ifdefDeclares: Map[String, ArrayBuffer[Seq[Any]]]
- val ifdefInitials: Map[String, ArrayBuffer[Seq[Any]]]
- def initialize(e: Expression, reset: Expression, init: Expression): Any
- def initialize_mem(s: DefMemory, opt: MemoryEmissionOption): Unit
- val initials: ArrayBuffer[Seq[Any]]
- val instdeclares: ArrayBuffer[Seq[Any]]
- def invalidAssign(e: Expression): ArrayBuffer[Seq[Any]]
-
final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- var maxMemSize: BigInt
- val memoryInitials: ArrayBuffer[Seq[Any]]
- val moduleTarget: ModuleTarget
- val namespace: Namespace
-
final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- val netlist: LinkedHashMap[WrappedExpression, InfoExpr]
- val noResetAlwaysBlocks: LinkedHashMap[Expression, ArrayBuffer[Seq[Any]]]
-
final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- val portdefs: ArrayBuffer[Seq[Any]]
- def printf(str: StringLit, args: Seq[Expression]): Seq[Any]
- def rand_string(t: Type): Seq[Any]
- def rand_string(t: Type, ifdef: String): Seq[Any]
- def rand_string(t: Type, ifdefOpt: Option[String]): Seq[Any]
- def regUpdate(r: Expression, clk: Expression, reset: Expression, init: Expression): ArrayBuffer[_ >: Seq[Any] with (Expression, Expression, Seq[Any]) <: Equals]
- def simulate(clk: Expression, en: Expression, s: Seq[Any], cond: Option[String], info: Info): ArrayBuffer[Seq[Any]]
- val simulates: ArrayBuffer[Seq[Any]]
- def stop(ret: Int): Seq[Any]
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
-
def
toString(): String
- Definition Classes
- AnyRef → Any
- def update(e: Expression, value: Expression, clk: Expression, en: Expression, info: Info): ArrayBuffer[Seq[Any]]
-
final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()
-
final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
This is the documentation for Firrtl.