object Reg
Utility for constructing hardware registers
The width of a Reg (inferred or not) is copied from the type template
val r0 = Reg(UInt()) // width is inferred val r1 = Reg(UInt(8.W)) // width is set to 8 val r2 = Reg(Vec(4, UInt())) // width is inferred val r3 = Reg(Vec(4, UInt(8.W))) // width of each element is set to 8 class MyBundle { val unknown = UInt() val known = UInt(8.W) } val r4 = Reg(new MyBundle) // Width of r4.unknown is inferred // Width of r4.known is set to 8
- Source
- Reg.scala
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Construct a Reg from a type template with no initialization value (reset is ignored).
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.