object ShiftRegister extends ShiftRegisterIntf
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- Reg.scala
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- def _applyImpl[T <: Data](in: T, n: Int, resetData: T, en: Bool)(implicit sourceInfo: SourceInfo): T
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- def _applyImpl[T <: Data](in: T, n: Int, en: Bool = true.B)(implicit sourceInfo: SourceInfo): T
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- macro def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T
Returns the n-cycle delayed version of the input signal with reset initialization.
Returns the n-cycle delayed version of the input signal with reset initialization.
- in
input to delay
- n
number of cycles to delay
- resetData
reset value for each register in the shift
- en
enable the shift
- Definition Classes
- ShiftRegisterIntf
val regDelayTwoReset = ShiftRegister(nextVal, 2, 0.U, ena)
Example: - macro def apply[T <: Data](in: T, n: Int): T
Returns the n-cycle delayed version of the input signal.
Returns the n-cycle delayed version of the input signal.
Enable is assumed to be true.
- in
input to delay
- n
number of cycles to delay
- Definition Classes
- ShiftRegisterIntf
val regDelayTwo = ShiftRegister(nextVal, 2)
Example: - macro def apply[T <: Data](in: T, n: Int, en: Bool): T
Returns the n-cycle delayed version of the input signal.
Returns the n-cycle delayed version of the input signal.
- in
input to delay
- n
number of cycles to delay
- en
enable the shift
- Definition Classes
- ShiftRegisterIntf
val regDelayTwo = ShiftRegister(nextVal, 2, ena)
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- ShiftRegisterIntf
- def do_apply[T <: Data](in: T, n: Int)(implicit sourceInfo: SourceInfo): T
- Definition Classes
- ShiftRegisterIntf
- def do_apply[T <: Data](in: T, n: Int, en: Bool = true.B)(implicit sourceInfo: SourceInfo): T
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- ShiftRegisterIntf
- def do_mem[T <: Data](in: T, n: Int, en: Bool, useDualPortSram: Boolean, name: Option[String])(implicit sourceInfo: SourceInfo): T
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- macro def mem[T <: Data](in: T, n: Int, en: Bool, useDualPortSram: Boolean, name: Option[String]): T
Returns the n-cycle delayed version of the input signal (SyncReadMem-based ShiftRegister implementation).
Returns the n-cycle delayed version of the input signal (SyncReadMem-based ShiftRegister implementation).
- in
input to delay
- n
number of cycles to delay
- en
enable the shift
- useDualPortSram
dual port or single port SRAM based implementation
- name
name of SyncReadMem object
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- ShiftRegisterIntf
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.