package memlib

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Visibility
  1. Public
  2. All

Type Members

  1. class ConfWriter extends AnyRef
  2. case class Config(pin: Pin, source: Source, top: Top) extends Product with Serializable
  3. class CreateMemoryAnnotations extends Transform with DependencyAPIMigration with PreservesAll[Transform]
  4. case class DefAnnotatedMemory(info: Info, name: String, dataType: Type, depth: BigInt, writeLatency: Int, readLatency: Int, readers: Seq[String], writers: Seq[String], readwriters: Seq[String], readUnderWrite: ir.ReadUnderWrite.Value, maskGran: Option[BigInt], memRef: Option[(String, String)]) extends Statement with IsDeclaration with Product with Serializable
  5. class InferReadWrite extends Transform with DependencyAPIMigration with PreservesAll[Transform] with SeqTransformBased with HasShellOptions
  6. case class MemConf(name: String, depth: BigInt, width: Int, ports: Map[MemPort, Int], maskGranularity: Option[Int]) extends Product with Serializable
  7. class MemDelayAndReadwriteTransformer extends AnyRef

    This class performs the primary work of the transform: splitting readwrite ports into separate read and write ports while simultaneously compiling memory latencies to combinational-read memories with delay pipelines.

    This class performs the primary work of the transform: splitting readwrite ports into separate read and write ports while simultaneously compiling memory latencies to combinational-read memories with delay pipelines. It is represented as a class that takes a module as a constructor argument, as it encapsulates the mutable state required to analyze and transform one module.

    Note

    The final transformed module is found in the (sole public) field transformed

  8. class MemLibOptions extends RegisteredLibrary
  9. sealed abstract class MemPort extends AnyRef
  10. case class NoDedupMemAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] with Product with Serializable

    A component, e.g.

    A component, e.g. register etc. Must be declared only once under the TopAnnotation

  11. sealed trait PassOption extends AnyRef
  12. case class Pin(name: String) extends Product with Serializable
  13. case class PinAnnotation(pins: Seq[String]) extends NoTargetAnnotation with Product with Serializable

    Annotates the name of the pins to add for WiringTransform

  14. class ReplSeqMem extends Transform with HasShellOptions with DependencyAPIMigration with PreservesAll[Transform]
  15. case class ReplSeqMemAnnotation(inputFileName: String, outputConfig: String) extends NoTargetAnnotation with Product with Serializable
  16. class ReplaceMemMacros extends Transform with DependencyAPIMigration with PreservesAll[Transform]

    Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file.

    Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file. This will not generate wmask ports if not needed. Creates the minimum # of black boxes needed by the design.

  17. class ResolveMemoryReference extends Transform with DependencyAPIMigration with PreservesAll[Transform]

    Resolves annotation ref to memories that exactly match (except name) another memory

  18. class SimpleMidTransform extends SimpleTransform
  19. case class Source(name: String, module: String) extends Product with Serializable
  20. case class Top(name: String) extends Product with Serializable
  21. class YamlFileReader extends AnyRef
  22. class YamlFileWriter extends AnyRef
  23. class SimpleTransform extends Transform
    Annotations
    @deprecated
    Deprecated

    (Since version FIRRTL 1.3) Migrate to a transform that does not take arguments. This will be removed in 1.4.

Value Members

  1. object AnalysisUtils
  2. object CustomYAMLProtocol extends DefaultYamlProtocol
  3. object DefAnnotatedMemory extends Serializable
  4. object InferReadWriteAnnotation extends NoTargetAnnotation with Product with Serializable
  5. object InferReadWritePass extends Pass
  6. object InputConfigFileName extends PassOption with Product with Serializable
  7. object MaskedReadWritePort extends MemPort with Product with Serializable
  8. object MaskedWritePort extends MemPort with Product with Serializable
  9. object MemConf extends Serializable
  10. object MemDelayAndReadwriteTransformer
  11. object MemPort
  12. object MemTransformUtils
  13. object OutputConfigFileName extends PassOption with Product with Serializable
  14. object PassCircuitName extends PassOption with Product with Serializable
  15. object PassConfigUtil
  16. object PassModuleName extends PassOption with Product with Serializable
  17. object ReadPort extends MemPort with Product with Serializable
  18. object ReadWritePort extends MemPort with Product with Serializable
  19. object RenameAnnotatedMemoryPorts extends Pass

    Changes memory port names to standard port names (i.e.

    Changes memory port names to standard port names (i.e. RW0 instead T_408)

  20. object ReplSeqMemAnnotation extends Serializable
  21. object ReplaceMemMacros
  22. object ResolveMaskGranularity extends Pass

    Determines if a write mask is needed (wmode/en and wmask are equivalent).

    Determines if a write mask is needed (wmode/en and wmask are equivalent). Populates the maskGran field of DefAnnotatedMemory Annotations:

    • maskGran = (dataType size) / (number of mask bits)
      • i.e. 1 if bitmask, 8 if bytemask, absent for no mask TODO(shunshou): Add floorplan info?
  23. object ToMemIR extends Pass

    Annotates sequential memories that are candidates for macro replacement.

    Annotates sequential memories that are candidates for macro replacement. Requirements for macro replacement:

    • read latency and write latency of one
    • only one readwrite port or write port
    • zero or one read port
    • undefined read-under-write behavior
  24. object VerilogMemDelays extends Pass
  25. object WritePort extends MemPort with Product with Serializable

Ungrouped