c

firrtl.ir

Module

case class Module(info: Info, name: String, ports: Seq[Port], body: Statement) extends DefModule with UseSerializer with Product with Serializable

Internal Module

An instantiable hardware block

Source
IR.scala
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. Module
  2. Serializable
  3. Serializable
  4. Product
  5. Equals
  6. UseSerializer
  7. DefModule
  8. IsDeclaration
  9. HasInfo
  10. HasName
  11. FirrtlNode
  12. AnyRef
  13. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new Module(info: Info, name: String, ports: Seq[Port], body: Statement)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  5. val body: Statement
  6. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  7. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  8. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  9. def foreachInfo(f: (Info) ⇒ Unit): Unit
    Definition Classes
    ModuleDefModule
  10. def foreachPort(f: (Port) ⇒ Unit): Unit
    Definition Classes
    ModuleDefModule
  11. def foreachStmt(f: (Statement) ⇒ Unit): Unit
    Definition Classes
    ModuleDefModule
  12. def foreachString(f: (String) ⇒ Unit): Unit
    Definition Classes
    ModuleDefModule
  13. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  14. val info: Info
    Definition Classes
    ModuleDefModuleHasInfo
  15. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  16. def mapInfo(f: (Info) ⇒ Info): DefModule
    Definition Classes
    ModuleDefModule
  17. def mapPort(f: (Port) ⇒ Port): DefModule
    Definition Classes
    ModuleDefModule
  18. def mapStmt(f: (Statement) ⇒ Statement): DefModule
    Definition Classes
    ModuleDefModule
  19. def mapString(f: (String) ⇒ String): DefModule
    Definition Classes
    ModuleDefModule
  20. val name: String
    Definition Classes
    ModuleDefModuleHasName
  21. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  22. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  23. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  24. val ports: Seq[Port]
    Definition Classes
    ModuleDefModule
  25. def serialize: String
    Definition Classes
    UseSerializer → FirrtlNode
  26. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  27. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  28. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  29. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()

Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from UseSerializer

Inherited from DefModule

Inherited from IsDeclaration

Inherited from HasInfo

Inherited from HasName

Inherited from FirrtlNode

Inherited from AnyRef

Inherited from Any

Ungrouped