package memlib
- Alphabetic
- Public
- All
Type Members
- class ConfWriter extends AnyRef
- case class Config(pin: Pin, source: Source, top: Top) extends Product with Serializable
- class CreateMemoryAnnotations extends Transform with DependencyAPIMigration
- case class DefAnnotatedMemory(info: Info, name: String, dataType: Type, depth: BigInt, writeLatency: Int, readLatency: Int, readers: Seq[String], writers: Seq[String], readwriters: Seq[String], readUnderWrite: ir.ReadUnderWrite.Value, maskGran: Option[BigInt], memRef: Option[(String, String)]) extends Statement with IsDeclaration with Product with Serializable
- class InferReadWrite extends Transform with DependencyAPIMigration with SeqTransformBased with HasShellOptions
- case class MemConf(name: String, depth: BigInt, width: Int, ports: Map[MemPort, Int], maskGranularity: Option[Int]) extends Product with Serializable
-
class
MemDelayAndReadwriteTransformer extends AnyRef
This class performs the primary work of the transform: splitting readwrite ports into separate read and write ports while simultaneously compiling memory latencies to combinational-read memories with delay pipelines.
This class performs the primary work of the transform: splitting readwrite ports into separate read and write ports while simultaneously compiling memory latencies to combinational-read memories with delay pipelines. It is represented as a class that takes a module as a constructor argument, as it encapsulates the mutable state required to analyze and transform one module.
- Note
The final transformed module is found in the (sole public) field transformed
- class MemLibOptions extends RegisteredLibrary
- sealed abstract class MemPort extends AnyRef
-
case class
NoDedupMemAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] with Product with Serializable
A component, e.g.
A component, e.g. register etc. Must be declared only once under the TopAnnotation
- sealed trait PassOption extends AnyRef
- case class Pin(name: String) extends Product with Serializable
-
case class
PinAnnotation(pins: Seq[String]) extends NoTargetAnnotation with Product with Serializable
Annotates the name of the pins to add for WiringTransform
- class ReplSeqMem extends Transform with HasShellOptions with DependencyAPIMigration
- case class ReplSeqMemAnnotation(inputFileName: String, outputConfig: String) extends NoTargetAnnotation with Product with Serializable
-
class
ReplaceMemMacros extends Transform with DependencyAPIMigration
Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file.
Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file. This will not generate wmask ports if not needed. Creates the minimum # of black boxes needed by the design.
-
class
ResolveMemoryReference extends Transform with DependencyAPIMigration
Resolves annotation ref to memories that exactly match (except name) another memory
- class SimpleMidTransform extends SimpleTransform
- case class Source(name: String, module: String) extends Product with Serializable
- case class Top(name: String) extends Product with Serializable
- class YamlFileReader extends AnyRef
- class YamlFileWriter extends AnyRef
-
class
SimpleTransform extends Transform
- Annotations
- @deprecated
- Deprecated
(Since version FIRRTL 1.3) Migrate to a transform that does not take arguments. This will be removed in 1.4.
Value Members
- object AnalysisUtils
- object CustomYAMLProtocol extends DefaultYamlProtocol
- object DefAnnotatedMemory extends Serializable
- object InferReadWriteAnnotation extends NoTargetAnnotation with Product with Serializable
- object InferReadWritePass extends Pass
- object InputConfigFileName extends PassOption with Product with Serializable
- object MaskedReadWritePort extends MemPort with Product with Serializable
- object MaskedWritePort extends MemPort with Product with Serializable
- object MemConf extends Serializable
- object MemDelayAndReadwriteTransformer
- object MemPort
- object MemTransformUtils
- object OutputConfigFileName extends PassOption with Product with Serializable
- object PassCircuitName extends PassOption with Product with Serializable
- object PassConfigUtil
- object PassModuleName extends PassOption with Product with Serializable
- object ReadPort extends MemPort with Product with Serializable
- object ReadWritePort extends MemPort with Product with Serializable
-
object
RenameAnnotatedMemoryPorts extends Pass
Changes memory port names to standard port names (i.e.
Changes memory port names to standard port names (i.e. RW0 instead T_408)
- object ReplSeqMemAnnotation extends Serializable
- object ReplaceMemMacros
-
object
ResolveMaskGranularity extends Pass
Determines if a write mask is needed (wmode/en and wmask are equivalent).
Determines if a write mask is needed (wmode/en and wmask are equivalent). Populates the maskGran field of DefAnnotatedMemory Annotations:
- maskGran = (dataType size) / (number of mask bits)
- i.e. 1 if bitmask, 8 if bytemask, absent for no mask TODO(shunshou): Add floorplan info?
- maskGran = (dataType size) / (number of mask bits)
-
object
ToMemIR extends Pass
Annotates sequential memories that are candidates for macro replacement.
Annotates sequential memories that are candidates for macro replacement. Requirements for macro replacement:
- read latency and write latency of one
- only one readwrite port or write port
- zero or one read port
- undefined read-under-write behavior
- object VerilogMemDelays extends Pass
- object WritePort extends MemPort with Product with Serializable
This is the documentation for Firrtl.