S
LiteralBuilder core
SF
core
SFix
core SFixFactory
SFix2D
core
SFixCast
core
SFixFactory
core
SINGLE_RAM
core
SInt
IODirection LiteralBuilder Operator core SIntFactory
SIntFactory
core
SIntLiteral
core
SIntPimper
core
SYNC
core
SafeStack
core
SafeStackWithStackable
core
ScalaLocated
core
ScalaUniverse
core
Scope
core
Sel
core
Select
core
SeqMux
core
ShiftLeftByInt
BitVector Bits SInt UInt
ShiftLeftByIntFixedWidth
BitVector Bits SInt UInt
ShiftLeftByUInt
BitVector Bits SInt UInt
ShiftLeftByUIntFixedWidth
BitVector Bits SInt UInt
ShiftRightByInt
BitVector Bits SInt UInt
ShiftRightByIntFixedWidth
BitVector Bits SInt UInt
ShiftRightByUInt
BitVector Bits SInt UInt
SlicesCount
core
SlowArea
core
Smaller
SInt UInt
SmallerOrEqual
SInt UInt
Spinal
core
SpinalConfig
core
SpinalEnum
core
SpinalEnumCraft
core
SpinalEnumElement
core
SpinalEnumEncoding
core
SpinalError
core
SpinalExit
core
SpinalInfo
core
SpinalLog
core
SpinalMap
core
SpinalMode
core
SpinalProgress
core
SpinalReport
core
SpinalTag
core
SpinalTagReady
core
SpinalVerilog
core
SpinalVerilogBoot
core
SpinalVhdl
core
SpinalVhdlBoot
core
SpinalWarning
core
Stackable
core
StringToBits
core
StringToSInt
core
StringToUInt
core
Sub
BitVector SInt UInt
SwitchContext
core
SwitchStack
core
SwitchTreeCase
core
SwitchTreeDefault
core
SymplifyNode
core
SyncNode
core
sameAddressThan
MemReadSync
sameType
Attribute AttributeFlag AttributeString
scalaLocatedEnable
GlobalData
sec
BigDecimalBuilder DoubleBuilder IntBuilder
sensitivity
Process
seq
Sel
set
Bool OwnableRef
setAll
BitVector
setAllTo
BitVector
setAllocate
ArrayManager
setAssignementContext
AssignementTreePart BaseType MultipleAssignmentNode Reg WhenNode
setBlackBoxName
BlackBox
setClockDomain
SyncNode
setCompositeName
Nameable
setDataInput
Reg
setDefinitionName
Component
setInitialValue
Reg
setInput
AssertNode BaseType BinaryOperator BitAssignmentFixed BitAssignmentFloating Cast ConstantOperator ExtractBitsVectorFixed ExtractBitsVectorFloating ExtractBoolFixed ExtractBoolFloating Literal MemReadAsync MemReadSync MemReadWrite_readPart MemReadWrite_writePart MemWrite MultipleAssignmentNode Multiplexer Node NodeWithVariableInputsCount NodeWithoutInputs RangedAssignmentFixed RangedAssignmentFloating Reg Resize SyncNode UnaryOperator WhenNode
setName
Nameable
setPartialName
Nameable
setRefOwner
OwnableRef
setSyncronousWith
ClockDomain
setTechnology
Mem
setUseReset
SyncNode
setWeakName
Nameable
setWhen
Bool
setWidth
BitVector
severity
AssertNode
shell
SpinalConfig
shift
ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth
shiftLeftBitsByIntFixedWidthImpl
PhaseVhdl
shiftLeftBitsByUIntFixedWidthImpl
PhaseVhdl
shiftLeftByIntFixedWidthImpl
PhaseVerilog PhaseVhdl
shiftLeftByIntImpl
PhaseVerilog PhaseVhdl
shiftLeftByUIntFixedWidthImpl
PhaseVhdl
shiftLeftFixedWidthImpl
SymplifyNode
shiftLeftImpl
SymplifyNode
shiftLeftWidth
WidthInfer
shiftRightBitsByIntFixedWidthImpl
PhaseVhdl
shiftRightByIntFixedWidthImpl
PhaseVerilog PhaseVhdl
shiftRightByIntImpl
PhaseVerilog PhaseVhdl
shiftRightFixedWidthImpl
SymplifyNode
shiftRightImpl
SymplifyNode
shiftRightSignedByIntFixedWidthImpl
PhaseVerilog
shiftRightWidth
WidthInfer
short
ScalaLocated
signalCache
core
signalNeedProcess
PhaseVerilog
simplifyNode
Node Add And Equal Mul NotEqual Or ShiftLeftByInt ShiftLeftByIntFixedWidth ShiftLeftByUInt ShiftLeftByUIntFixedWidth ShiftRightByInt ShiftRightByIntFixedWidth ShiftRightByUInt Sub Xor Cat Not And Equal Not NotEqual Or Xor Equal NotEqual Minus Not Smaller SmallerOrEqual Not Smaller SmallerOrEqual ResizeBits ResizeSInt ResizeUInt
singleShot
SpinalVerilogBoot SpinalVhdlBoot
size
ExtractBitsVectorFloating Resize SafeStack
slices
BigIntBuilder IntBuilder
softReset
ClockDomain SyncNode
softResetActiveLevel
ClockDomainConfig
sortedComponents
PhaseContext
spinal
root
spinalEnum
SpinalEnumCraft SpinalEnumElement
spinalTags
SpinalTagReady
splitNewSink
SpinalTagReady
stack
SafeStack
startTime
Driver
subdivideIn
BitVector
swapEncoding
EnumEncoded InferableEnumEncodingImpl
switch
core
switchContext
CaseContext
switchStack
GlobalData
syncroneWith
ClockDomain