S
LiteralBuilder core
SFix
core
SFix2D
core
SFixCast
core
SINGLE_RAM
core
SInt
IODirection LiteralBuilder Operator core SIntFactory
SIntCast
core
SIntFactory
core
SIntPimper
core
STime
core
SYNC
core
SafeStack
core
SafeStackWithStackable
core
ScalaLocated
core
ScalaUniverse
core
Scope
core
Sel
core
SeqMux
core
ShiftLeftByInt
BitVector Bits SInt UInt
ShiftLeftByUInt
BitVector Bits SInt UInt
ShiftRightByInt
BitVector Bits SInt UInt
ShiftRightByUInt
BitVector Bits SInt UInt
Smaller
SInt UInt
SmallerOrEqual
SInt UInt
SpinalEnum
core
SpinalEnumCraft
core
SpinalEnumElement
core
SpinalEnumEncoding
core
SpinalError
core
SpinalExit
core
SpinalInfo
core
SpinalInfoPhase
core
SpinalLog
core
SpinalMap
core
SpinalTag
core
SpinalTagReady
core
SpinalVhdl
core
SpinalVhdlBuilder
core
SpinalWarning
core
Stackable
core
StringToBits
core
StringToSInt
core
StringToUInt
core
Sub
BitVector SInt UInt
SwitchContext
core
SwitchNode
core
SwitchStack
core
SwitchTree
VhdlBackend
SymplifyNode
core
SyncNode
Reg core
sameAddressThan
MemReadSync
sameType
Attribute AttributeFlag AttributeString
scalaLocatedEnable
GlobalData
sec
DoubleBuilder IntBuilder
seq
Sel
sequancial
core
set
Bool
setAll
BitVector
setAllTo
BitVector
setAllocate
ArrayManager
setAsBlackBox
Mem
setAssignementContext
AssignementTreePart BaseType MultipleAssignmentNode Reg WhenNode
setBlackBoxName
BlackBox
setCompositeName
Nameable
setDataInput
Reg
setDefaultClockFrequency
SpinalVhdlBuilder
setDefaultConfigForClockDomains
SpinalVhdlBuilder
setDefinitionName
Component
setEnumPackage
SpinalVhdlBuilder
setInitialValue
Reg
setInput
BaseType BinaryOperator BitAssignmentFixed BitAssignmentFloating Cast ConstantOperator ExtractBitsVectorFixed ExtractBitsVectorFloating ExtractBoolFixed ExtractBoolFloating Literal MemReadAsync MemReadSync MemWrite MemWriteOrRead_readPart MemWriteOrRead_writePart Multiplexer Node NodeWithVariableInputsCount NodeWithoutInputs RangedAssignmentFixed RangedAssignmentFloating Reg Resize SyncNode UnaryOperator WhenNode
setName
Nameable
setOutputFile
SpinalVhdlBuilder
setSpinalPackage
SpinalVhdlBuilder
setSyncronousWith
ClockDomain
setTbName
SpinalVhdlBuilder
setTbOutputFile
SpinalVhdlBuilder
setUseReset
SyncNode
setWeakName
Nameable
setWhen
Bool
setWidth
BitVector
shift
ShiftLeftByInt ShiftRightByInt
shiftLeftByIntImpl
VhdlBackend
shiftLeftImpl
SymplifyNode
shiftLeftWidth
WidthInfer
shiftRightByIntImpl
VhdlBackend
shiftRightImpl
SymplifyNode
shiftRightWidth
WidthInfer
short
ScalaLocated
signalCache
core
signedDivImpl
SymplifyNode
signedModImpl
SymplifyNode
simplifyBlacBoxGenerics
Backend
simplifyNode
Multiplexer Node Add And Div Equal Mod Mul NotEqual Or RotateLeftByUInt ShiftLeftByInt ShiftLeftByUInt ShiftRightByInt ShiftRightByUInt Sub Xor Cat Not And Equal Not NotEqual Or Xor Equal NotEqual Minus Not Smaller SmallerOrEqual Not Smaller SmallerOrEqual ResizeBits ResizeSInt ResizeUInt
simplifyNodes
Backend
size
ExtractBitsVectorFloating Resize SafeStack
sortedComponents
Backend
spinal
root
stack
SafeStack
startTime
Driver
switch
core
switch2
core
switchContext
CaseContext
switchStack
GlobalData
syncroneWith
ClockDomain