Generic
core
GlobalData
core
GlobalDataUser
core
genIf
Data
genNames
Generic
genSensitivity
Process
generate
SpinalConfig
generateVerilog
SpinalConfig
generateVhdl
SpinalConfig
generic
Ram_1c_1w_1ra Ram_1c_1w_1rs Ram_1wors Ram_1wrs
get
GlobalData
getAddress
MemReadAsync MemReadSync MemWrite MemWriteOrRead_readPart MemWriteOrRead_writePart
getAddressId
MemReadSync MemWrite MemWriteOrRead_readPart MemWriteOrRead_writePart
getAllIo
Component
getAssignedBits
AssignementNode BitAssignmentFixed BitAssignmentFloating RangedAssignmentFixed RangedAssignmentFloating
getAssignementContext
AssignementTreePart BaseType MultipleAssignmentNode Reg WhenNode
getAsyncProcesses
VhdlVerilogBase
getAsynchronousInputs
SyncNode
getBaseType
DontCareNode DontCareNodeFixed DontCareNodeInfered
getBitCount
ExtractBitsVectorFloating RangedAssignmentFloating
getBitId
BitAssignmentFixed BitAssignmentFloating ExtractBoolFixed ExtractBoolFloating
getBitVector
Extract ExtractBitsVectorFixed ExtractBitsVectorFloating ExtractBoolFixed ExtractBoolFloating
getBitsStringOn
BitsAllToLiteral BitsLiteral BoolLiteral
getBitsWidth
BaseType Data DataWrapper MultiData
getChipSelect
MemWriteOrRead_readPart MemWriteOrRead_writePart
getChipSelectId
MemWriteOrRead_readPart MemWriteOrRead_writePart
getClock
SyncNode
getClockDomain
SyncNode
getClockDomainDriver
ClockDomain
getClockDomainTag
ClockDomain
getClockEnable
SyncNode
getClockEnableId
SyncNode SyncNode
getClockInputId
SyncNode SyncNode
getClockResetId
SyncNode SyncNode
getComponent
Data
getComponents
Data
getData
MemReadAsync MemReadSync MemWrite MemWriteOrRead_readPart MemWriteOrRead_writePart
getDataId
MemWrite MemWriteOrRead_writePart
getDataInput
Reg
getDataInputId
RegS
getDisplayName
Component Nameable
getDrivingReg
BaseType
getElseNull
ArrayManager
getElseWhenChain
AssignementLevelWhen
getEnable
MemWrite
getEnableId
MemReadSync MemWrite
getEnumDebugType
PhaseVerilog PhaseVhdl
getEnumToDebugFuntion
PhaseVerilog PhaseVhdl
getErrorCount
SpinalError
getGeneric
BlackBox
getGroupedIO
Component
getHi
ExtractBitsVectorFixed RangedAssignmentFixed
getInitialValue
Reg
getInitialValueId
RegS
getInput
AssertNode BaseType BinaryOperator BitAssignmentFixed BitAssignmentFloating Cast ConstantOperator ExtractBitsVectorFixed ExtractBitsVectorFloating ExtractBoolFixed ExtractBoolFloating Literal MemReadAsync MemReadSync MemWrite MemWriteOrRead_readPart MemWriteOrRead_writePart Multiplexer Node NodeWithVariableInputsCount NodeWithoutInputs RangedAssignmentFixed RangedAssignmentFloating Reg Resize SyncNode UnaryOperator WhenNode
getInputData
Extract ExtractBitsVectorFixed ExtractBitsVectorFloating ExtractBoolFixed ExtractBoolFloating
getInputs
AssertNode BaseType BinaryOperator BitAssignmentFixed BitAssignmentFloating Cast ConstantOperator ExtractBitsVectorFixed ExtractBitsVectorFloating ExtractBoolFixed ExtractBoolFloating Literal MemReadAsync MemReadSync MemWrite MemWriteOrRead_readPart MemWriteOrRead_writePart Multiplexer Node NodeWithVariableInputsCount NodeWithoutInputs RangedAssignmentFixed RangedAssignmentFloating Reg Resize SyncNode UnaryOperator WhenNode
getInputsCount
AssertNode BaseType BinaryOperator BitAssignmentFixed BitAssignmentFloating Cast ConstantOperator ExtractBitsVectorFixed ExtractBitsVectorFloating ExtractBoolFixed ExtractBoolFloating Literal MemReadAsync MemReadSync MemWrite MemWriteOrRead_readPart MemWriteOrRead_writePart Multiplexer Node NodeWithVariableInputsCount NodeWithoutInputs RangedAssignmentFixed RangedAssignmentFloating Reg Resize SyncNode UnaryOperator WhenNode
getInstanceCounter
GlobalData
getLatency
SyncNode
getLiteralFactory
And Mul RotateLeftByUInt ShiftLeftByInt ShiftLeftByUInt Sub And RotateLeftByUInt ShiftLeftByInt ShiftLeftByUInt And Mul ShiftLeftByInt ShiftLeftByUInt Sub And Mul ShiftLeftByInt ShiftLeftByUInt Sub
getLo
ExtractBitsVectorFixed RangedAssignmentFixed
getMask
MemWrite
getMaskId
MemWrite
getMax
FixedFrequency IClockDomainFrequency UnknownFrequency
getMem
MemReadAsync MemReadSync MemWrite MemWriteOrRead_readPart MemWriteOrRead_writePart
getMin
FixedFrequency IClockDomainFrequency UnknownFrequency
getName
Attribute AttributeFlag AttributeString Nameable NameableByComponent
getOffset
ExtractBitsVectorFloating RangedAssignmentFloating
getOutBaseType
AssignementNode BitAssignmentFixed BitAssignmentFloating RangedAssignmentFixed RangedAssignmentFloating
getOutputByConsumers
Reg
getParameterNodes
Extract ExtractBitsVectorFixed ExtractBitsVectorFloating ExtractBoolFixed ExtractBoolFloating
getParentsPath
Component
getPath
Component
getReEncodingFuntion
PhaseVerilog PhaseVhdl
getReadEnable
MemReadSync
getReset
SyncNode
getResetStyleInputs
Reg SyncNode
getRootParent
Data
getScopeBits
AssignementNode BitAssignmentFixed BitAssignmentFloating RangedAssignmentFixed RangedAssignmentFloating
getSensitivity
VhdlVerilogBase
getSwappedEncoding
VerilogBase
getSynchronousInputs
MemReadSync MemWrite MemWriteOrRead_readPart MemWriteOrRead_writePart Reg SyncNode
getTag
SpinalTagReady
getThrowable
GlobalData
getValue
FixedFrequency IClockDomainFrequency SpinalEnumEncoding UnknownFrequency binaryOneHot binarySequancial native
getWhensCond
when
getWidth
Node SpinalEnumEncoding binaryOneHot binarySequancial native
getWidthNoInferation
BitVector
getWidthStringNoInferation
BitVector
getWriteEnable
MemWriteOrRead_readPart MemWriteOrRead_writePart
getWriteEnableId
MemWriteOrRead_readPart MemWriteOrRead_writePart
getZero
Bits Bool Data DataWrapper MultiData SInt SpinalEnumCraft UInt
getZeroUnconstrained
BitVector Bits SInt UInt
globalData
GlobalDataUser PhaseContext
globalScope
PhaseContext