Clock signal that defines the domain
Reset signal. If a register exists which needs a reset and the clock domain doesn’t provide one, an error message will be displayed.
Reset which infers an additional synchronous reset
Disable the clock on the whole clock domain without having to manually implement that on each synchronous element.
Specify the polarity of signals and the nature of the reset.
Allows you to specify the frequency of the given clock domain and later read it in your design. This parameter does not generate a PLL or more hardware to control the frequency.
Clock signal that defines the domain
Disable the clock on the whole clock domain without having to manually implement that on each synchronous element.
Specify the polarity of signals and the nature of the reset.
Allows you to specify the frequency of the given clock domain and later read it in your design.
Allows you to specify the frequency of the given clock domain and later read it in your design. This parameter does not generate a PLL or more hardware to control the frequency.
Slow down the current clock to factor time
Reset signal.
Reset signal. If a register exists which needs a reset and the clock domain doesn’t provide one, an error message will be displayed.
Reset which infers an additional synchronous reset
(Since version 1.3.0) Use copy instead of clone
(Since version ) see corresponding Javadoc for more information.
(Since version SpinalHDL 1.2.3) misspelled method will be removed
Represents the combined clock and reset signals for an hardware domain.
Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain. Clock domain application work like a stack, which mean, if you are in a given clock domain, you can still apply another clock domain locally.
Clock signal that defines the domain
Reset signal. If a register exists which needs a reset and the clock domain doesn’t provide one, an error message will be displayed.
Reset which infers an additional synchronous reset
Disable the clock on the whole clock domain without having to manually implement that on each synchronous element.
Specify the polarity of signals and the nature of the reset.
Allows you to specify the frequency of the given clock domain and later read it in your design. This parameter does not generate a PLL or more hardware to control the frequency.
clock domains documentation