Class

spinal.core

ClockDomainConfig

Related Doc: package core

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case class ClockDomainConfig(clockEdge: EdgeKind = RISING, resetKind: ResetKind = ASYNC, resetActiveLevel: Polarity = HIGH, softResetActiveLevel: Polarity = HIGH, clockEnableActiveLevel: Polarity = HIGH) extends Product with Serializable

The caracteristic (rising, async, high, e.g.) of the control signals of a ClockDomain

clockEdge

can be RISING (default) or FALLING

resetKind

can be ASYNC (default), SYNC or BOOT which is supported by some FPGAs (where FF values are loaded by the bitstream)

resetActiveLevel

can be HIGH (default), or LOW

softResetActiveLevel

can be HIGH (default), or LOW

clockEnableActiveLevel

can be HIGH (default), or LOW

See also

Clock domain documentation

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Instance Constructors

  1. new ClockDomainConfig(clockEdge: EdgeKind = RISING, resetKind: ResetKind = ASYNC, resetActiveLevel: Polarity = HIGH, softResetActiveLevel: Polarity = HIGH, clockEnableActiveLevel: Polarity = HIGH)

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    clockEdge

    can be RISING (default) or FALLING

    resetKind

    can be ASYNC (default), SYNC or BOOT which is supported by some FPGAs (where FF values are loaded by the bitstream)

    resetActiveLevel

    can be HIGH (default), or LOW

    softResetActiveLevel

    can be HIGH (default), or LOW

    clockEnableActiveLevel

    can be HIGH (default), or LOW

Value Members

  1. final def !=(arg0: Any): Boolean

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  2. final def ##(): Int

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  3. final def ==(arg0: Any): Boolean

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  4. final def asInstanceOf[T0]: T0

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  5. val clockEdge: EdgeKind

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    can be RISING (default) or FALLING

  6. val clockEnableActiveLevel: Polarity

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    can be HIGH (default), or LOW

  7. def clone(): AnyRef

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  8. final def eq(arg0: AnyRef): Boolean

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  9. final def getClass(): Class[_]

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  10. final def isInstanceOf[T0]: Boolean

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  11. final def ne(arg0: AnyRef): Boolean

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  12. final def notify(): Unit

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  13. final def notifyAll(): Unit

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  14. val resetActiveLevel: Polarity

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    can be HIGH (default), or LOW

  15. def resetAssertValue: Bool

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  16. val resetKind: ResetKind

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    can be ASYNC (default), SYNC or BOOT which is supported by some FPGAs (where FF values are loaded by the bitstream)

  17. val softResetActiveLevel: Polarity

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    can be HIGH (default), or LOW

  18. final def synchronized[T0](arg0: ⇒ T0): T0

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  19. val useResetPin: Boolean

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  20. final def wait(arg0: Long, arg1: Int): Unit

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  21. final def wait(arg0: Long): Unit

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  22. final def wait(): Unit

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Deprecated Value Members

  1. def finalize(): Unit

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    @Deprecated @deprecated @throws( classOf[java.lang.Throwable] )
    Deprecated

    (Since version ) see corresponding Javadoc for more information.

Inherited from Serializable

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Inherited from Product

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