StreamFifo

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

var _spinalTags: LinkedHashSet[SpinalTag]

def addAttribute(attribute: Attribute): StreamFifo.this.type

def addAttribute(name: String, value: Int): StreamFifo.this.type

def addAttribute(name: String, value: String): StreamFifo.this.type

def addAttribute(name: String): StreamFifo.this.type

def addComment(str: String): Component

def addPrePopTask(task: () ⇒ Unit): ArrayBuffer[PrePopTask]

def addTag[T <: SpinalTag](spinalTag: T): StreamFifo.this.type

def addTags(h: SpinalTag, tail: SpinalTag*): StreamFifo.this.type

def addTags[T <: SpinalTag](tags: Iterable[T]): StreamFifo.this.type

def afterElaboration(body: ⇒ Unit): ArrayBuffer[PrePopTask]

val allowExtraMsb: Boolean

def asFormalDut(): StreamFifo.this.type

final def asInstanceOf[T0]: T0

val bypass: Area

val children: ArrayBuffer[Component]

val clockDomain: Handle[ClockDomain]

def clone(): AnyRef

def component: Component

val dataType: HardType[T]

val definition: $anon forSome {type $anon <: SpinalTagReady { def addComment(str: String): $anon }}

var definitionName: String

var definitionNameNoMerge: Boolean

val depth: Int

Number of element stored in the fifo, Note that if withAsyncRead==false, then one extra transaction can be stored.

val dslBody: ScopeStatement

final def eq(arg0: AnyRef): Boolean

def equals(obj: Any): Boolean

def existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean

def filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]

def findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]

val forFMax: Boolean

Tune the design to get the maximal clock frequency.

def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit

def foreachTag(body: (SpinalTag) ⇒ Unit): Unit

def formalCheckLastPush(cond: (T) ⇒ Bool): Bool

def formalCheckOutputStage(cond: (T) ⇒ Bool): Bool

def formalCheckRam(cond: (T) ⇒ Bool): Vec[Bool]

def formalContains(cond: (T) ⇒ Bool): Bool

def formalContains(word: T): Bool

def formalCount(cond: (T) ⇒ Bool): UInt

def formalCount(word: T): UInt

def formalFullToEmpty(): Area { val was_full: spinal.core.Bool }

def getAllIo: Set[BaseType]

final def getClass(): Class[_]

def getDisplayName(): String

def getGroupedIO(ioBundleBypass: Boolean): Seq[Data]

def getInstanceCounter: Int

def getMode: Byte

def getName(default: String): String

def getName(): String

def getOrdredNodeIo: List[BaseType]

def getParentsPath(sep: String): String

def getPartialName(): String

def getPath(sep: String): String

def getPath(from: Component, to: Component): Seq[Component]

def getRefOwnersChain(): List[Any]

def getRtlPath(separator: String): String

def getScalaLocationLong: String

def getScalaLocationShort: String

def getScalaTrace(): Throwable

def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]

def getTags(): LinkedHashSet[SpinalTag]

def getTagsOf[T <: SpinalTag]()(implicit tag: ClassTag[T]): Iterable[T]

var globalData: GlobalData

def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean

def hasTag(spinalTag: SpinalTag): Boolean

def hashCode(): Int

def instanceAttributes(language: Language): Iterable[Attribute]

def instanceAttributes: Iterable[Attribute]

val io: Bundle with StreamFifoInterface[T] { ... /* 5 definitions in type refinement */ }

def isCompletelyUnnamed: Boolean

def isEmptyOfTag: Boolean

var isFormalTester: Boolean

final def isInstanceOf[T0]: Boolean

def isLogicLess: Boolean

final def isNamed: Boolean

def isPriorityApplicable(namePriority: Byte): Boolean

def isUnnamed: Boolean

var localNamingScope: NamingScope

val logic: Area { ... /* 6 definitions in type refinement */ }

def makeInputsAnyseq(): Unit

var name: String

var nameableRef: Nameable

final def ne(arg0: AnyRef): Boolean

def noIoPrefix(): StreamFifo.this.type

final def notify(): Unit

final def notifyAll(): Unit

def onBody[T](body: ⇒ T): T

def onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit

val oneStage: Area { ... /* 2 definitions in type refinement */ }

def overrideLocalName(name: String): StreamFifo.this.type

def parent: Component

var parentScope: ScopeStatement

def parents(of: Component, list: List[Component]): List[Component]

def postInitCallback(): StreamFifo.this.type

def postPopEvent(): Unit

def postPushEvent(): Unit

def prePop(): Unit

def prePopEvent(): Unit

var pulledDataCache: Map[Data, Data]

var refOwner: RefOwnerType

def reflectBaseType(name: String): BaseType

def reflectNames(): Unit

def removeTag(spinalTag: SpinalTag): StreamFifo.this.type

def removeTags(tags: Iterable[SpinalTag]): StreamFifo.this.type

def rework[T](gen: ⇒ T): T

var scalaTrace: Throwable

val scopeProperties: Capture

def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): StreamFifo.this.type

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): StreamFifo.this.type

def setCompositeName(nameable: Nameable, postfix: String): StreamFifo.this.type

def setCompositeName(nameable: Nameable, namePriority: Byte): StreamFifo.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): StreamFifo.this.type

def setCompositeName(nameable: Nameable): StreamFifo.this.type

def setDefinitionName(name: String, noMerge: Boolean): StreamFifo.this.type

def setFormalTester(): Unit

def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): StreamFifo.this.type

def setName(name: String, namePriority: Byte): StreamFifo.this.type

def setName(name: String, weak: Boolean): StreamFifo.this.type

def setName(name: String): StreamFifo.this.type

def setNameAsWeak(): StreamFifo.this.type

def setPartialName(name: String, namePriority: Byte, owner: Any): StreamFifo.this.type

def setPartialName(name: String, namePriority: Byte): StreamFifo.this.type

def setPartialName(name: String, weak: Boolean): StreamFifo.this.type

def setPartialName(owner: Nameable, name: String, namePriority: Byte): StreamFifo.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): StreamFifo.this.type

def setPartialName(name: String): StreamFifo.this.type

def setPartialName(owner: Nameable, name: String): StreamFifo.this.type

def setPartialName(owner: Nameable): StreamFifo.this.type

def setRefOwner(that: Any): Unit

def setScalaLocated(source: ScalaLocated): StreamFifo.this.type

def setWeakName(name: String): StreamFifo.this.type

def spinalTags: LinkedHashSet[SpinalTag]

def stub(): StreamFifo.this.type

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

def traceDisable(recursive: Boolean): StreamFifo.this.type

def traceEnable(recursive: Boolean): StreamFifo.this.type

var traceEnabled: Boolean

def unsetName(): StreamFifo.this.type

val useVec: Boolean

Use an Vec of register instead of a Mem to store the content Only available if withAsyncRead == true.

val userCache: Map[Any, Any]

def valCallback[T](ref: T, name: String): T

def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit

def valCallbackRec(ref: Any, name: String): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def walkComponents(body: (Component) ⇒ Unit): Unit

val withAsyncRead: Boolean

Read the memory using asynchronous read port (ex distributed ram).

def withAutoPull(): Unit

val withBypass: Boolean

Bypass the push port to the pop port when the fifo is empty.If false, add 1 cycle latency.

val withExtraMsb: Boolean

var withHierarchyAutoPull: Boolean

def withKeywords(): Unit

var withVitalOutputs: Boolean

def withoutKeywords(): Unit

var withoutReservedKeywords: Boolean

def finalize(): Unit