BlackBox
Related Doc:
package chisel3
(Since version Chisel 3.4)
This must wrap the datatype used to set the io field of any Module.
This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])
Items in [] are optional.
The granted iodef must be a chisel type and not be bound to hardware.
Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.
TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.
Compatibility function.
Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.
Should NOT be used elsewhere. This API will NOT last.
TODO: remove this, perhaps by removing Bindings checks in compatibility mode.
Computes the name of this HasId, if one exists
Computes the name of this HasId, if one exists
Optionally provide a default prefix for computing the name
Optionally provide default seed for computing the name
the name, if it can be computed
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The name of a module approximates the behavior of the Java Reflection method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:
- Anonymous modules will get an "_Anon" tag
- Modules defined in functions will use their class name and not a numeric name
If you want a custom or parametric name, override this method.
Whether either autoName or suggestName has been called
Signal name (for simulation).
Signal name (for simulation).
Legalized name of this module.
Legalized name of this module.
Called at the Module.apply(...) level after this Module has finished elaborating.
Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.
Helper method.
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.
The seed for the name of this component
this object
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
Should not be called until circuit elaboration is complete
Returns a FIRRTL ModuleName that references this object
Returns a FIRRTL ModuleName that references this object
Should not be called until circuit elaboration is complete
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
Should not be called until circuit elaboration is complete
Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.
Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:
To instantiate it, a BlackBox can be used like following:
The parameters API is experimental and may change