Resolved directions for both leaf and container nodes, only visible after a node is bound (since higher-level specifications like Input and Output can override directions).
An abstract class for data types that solely consist of (are an aggregate of) other Data objects.
Data type representing asynchronous reset signals
Data type representing asynchronous reset signals
These signals are similar to Clocks in that they must be glitch-free for proper circuit operation. Regs defined with the implicit reset being an AsyncReset will be asychronously reset registers.
Format bits as Binary
A data type for values represented by a single bitvector.
A data type for values represented by a single bitvector. This provides basic bitwise operations.
Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog.
Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.
Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT")) ibufds ( .IB(ibufds_IB), .I(ibufds_I), .O(ibufds_O) );
To instantiate it, a BlackBox can be used like following:
import chisel3._ import chisel3.experimental._ // Example with Xilinx differential buffer IBUFDS class IBUFDS extends BlackBox(Map("DIFF_TERM" -> "TRUE", // Verilog parameters "IOSTANDARD" -> "DEFAULT" )) { val io = IO(new Bundle { val O = Output(Clock()) // IO names will be the same val I = Input(Clock()) // (without 'io_' in prefix) val IB = Input(Clock()) // }) }
The parameters API is experimental and may change
A data type for booleans, defined as a single bit indicating true or false.
Base class for data types defined as a bundle of other data types.
Base class for data types defined as a bundle of other data types.
Usage: extend this class (either as an anonymous or named class) and define members variables of Data subtypes to be elements in the Bundle.
Example of an anonymous IO bundle
class MyModule extends Module { val io = IO(new Bundle { val in = Input(UInt(64.W)) val out = Output(SInt(128.W)) }) }
Or as a named class
class Packet extends Bundle { val header = UInt(16.W) val addr = UInt(16.W) val data = UInt(32.W) } class MyModule extends Module { val io = IO(new Bundle { val inPacket = Input(new Packet) val outPacket = Output(new Packet) }) val reg = Reg(new Packet) reg <> io.inPacket io.outPacket <> reg }
Format bits as Character
This forms the root of the type system for wire data types.
This forms the root of the type system for wire data types. The data value must be representable as some number (need not be known at Chisel compile time) of bits, and must have methods to pack / unpack structured data to / from bits.
Format bits as Decimal
Element is a leaf data type: it cannot contain other Data objects.
Element is a leaf data type: it cannot contain other Data objects. Example uses are for representing primitive data types, like integers and bits.
A function expected a Chisel type but got a hardware object
A function expected a hardware object but got a Chisel type
Superclass for Firrtl format specifiers for Bits
Put full name within parent namespace (eg.
Put full name within parent namespace (eg. bundleName.field)
Format bits as Hexidecimal
Mix-in for Bundles that have arbitrary Seqs of Chisel types that aren't involved in hardware construction.
Mix-in for Bundles that have arbitrary Seqs of Chisel types that aren't involved in hardware construction.
Used to avoid raising an error/exception when a Seq is a public member of the bundle. This is useful if we those public Seq fields in the Bundle are unrelated to hardware construction.
A combinational/asynchronous-read, sequential/synchronous-write memory.
A combinational/asynchronous-read, sequential/synchronous-write memory.
Writes take effect on the rising clock edge after the request. Reads are combinational (requests will return data on the same cycle). Read-after-write hazards are not an issue.
when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)
An aggregate had a mix of specified and unspecified directionality children
Used by Chisel Aspects to inject Chisel code into modules, after they have been elaborated.
Used by Chisel Aspects to inject Chisel code into modules, after they have been elaborated. This is an internal API - don't use!
It adds itself as an aspect to the module, which allows proper checking of connection and binding legality.
Abstract base class for Modules, which behave much like Verilog modules.
Abstract base class for Modules, which behave much like Verilog modules. These may contain both logic and state which are written in the Module body (constructor). This abstract base class includes an implicit clock and reset.
Module instantiations must be wrapped in a Module() call.
Put innermost name (eg.
Put innermost name (eg. field of bundle)
Abstract trait defining operations available on numeric-like hardware data types.
Abstract trait defining operations available on numeric-like hardware data types.
the underlying type of the number
NumbObject has a lot of convenience methods for converting between BigInts and Double and BigDecimal For backwards compatibility this is used with FixedPoint and Interval objects but is better used with the Num Object
Wrapper for printing Scala Strings
Superclass of things that can be printed in the resulting circuit
Superclass of things that can be printed in the resulting circuit
Usually created using the custom string interpolator p"..."
. Printable string interpolation is
similar to String
interpolation in Scala For example:
printf(p"The value of wire = $wire\n")
This is equivalent to writing:
printf(p"The value of wire = %d\n", wire)
All Chisel data types have a method .toPrintable
that gives a default pretty print that can be
accessed via p"..."
. This works even for aggregate types, for example:
val myVec = VecInit(5.U, 10.U, 13.U) printf(p"myVec = $myVec\n") // myVec = Vec(5, 10, 13) val myBundle = Wire(new Bundle { val foo = UInt() val bar = UInt() }) myBundle.foo := 3.U myBundle.bar := 11.U printf(p"myBundle = $myBundle\n") // myBundle = Bundle(a -> 3, b -> 11)
Users can override the default behavior of .toPrintable
in custom Bundle and Record
types.
Implicit for custom Printable string interpolator
Abstract base class for Modules that contain Chisel RTL.
Abstract base class for Modules that contain Chisel RTL. This abstract base class is a user-defined module which does not include implicit clock and reset and supports multiple IO() declarations.
Attempted to re-bind an already bound (directionality or hardware) object
Base class for Aggregates based on key values pairs of String and Data
Base class for Aggregates based on key values pairs of String and Data
Record should only be extended by libraries and fairly sophisticated generators. RTL writers should use Bundle. See Record#elements for an example.
"Abstract" Reset Type inferred in FIRRTL to either AsyncReset or Bool
"Abstract" Reset Type inferred in FIRRTL to either AsyncReset or Bool
This shares a common interface with AsyncReset and Bool but is not their actual super type due to Bool inheriting from abstract class UInt
A data type for signed integers, represented as a binary bitvector.
A data type for signed integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.
User-specified directions.
A sequential/synchronous-read, sequential/synchronous-write memory.
A sequential/synchronous-read, sequential/synchronous-write memory.
Writes take effect on the rising clock edge after the request. Reads return data on the rising edge after the request. Read-after-write behavior (when a read and write to the same address are requested on the same cycle) is undefined.
when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)
A data type for unsigned integers, represented as a binary bitvector.
A data type for unsigned integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.
A vector (array) of Data elements.
A vector (array) of Data elements. Provides hardware versions of various collection transformation functions found in software array implementations.
Careful consideration should be given over the use of Vec vs Seq or some other Scala collection. In general Vec only needs to be used when there is a need to express the hardware collection in a Reg or IO Bundle or when access to elements of the array is indexed via a hardware signal.
Example of indexing into a Vec using a hardware address and where the Vec is defined in an IO Bundle
val io = IO(new Bundle { val in = Input(Vec(20, UInt(16.W))) val addr = Input(UInt(5.W)) val out = Output(UInt(16.W)) }) io.out := io.in(io.addr)
type of elements
A trait for Vecs containing common hardware generators for collection operations.
A WhenContext may represent a when, and elsewhen, or an otherwise.
A WhenContext may represent a when, and elsewhen, or an otherwise. Since FIRRTL does not have an "elsif" statement, alternatives must be mapped to nested if-else statements inside the alternatives of the preceeding condition. In order to emit proper FIRRTL, it is necessary to keep track of the depth of nesting of the FIRRTL whens. Due to the "thin frontend" nature of Chisel3, it is not possible to know if a when or elsewhen has a succeeding elsewhen or otherwise; therefore, this information is added by preprocessing the command queue.
These implicit classes allow one to convert scala.Int or scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
These implicit classes allow one to convert scala.Int or scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. The versions .asUInt(width)|.asSInt(width) are also available to explicitly mark a width for the new literal.
Also provides .asBool to scala.Boolean and .asUInt to String
Note that, for stylistic reasons, one should avoid extracting immediately after this call using apply, ie. 0.asUInt(1)(0) due to potential for confusion (the 1 is a bit length and the 0 is a bit extraction position). Prefer storing the result and then extracting from it.
Implementation note: the empty parameter list (like U()
) is necessary to prevent
interpreting calls that have a non-Width parameter as a chained apply, otherwise things like
0.asUInt(16)
(instead of 16.W
) compile without error and produce undesired results.
This object was generated by sbt-buildinfo.
Input, Output, and Flipped are used to define the directions of Module IOs.
Input, Output, and Flipped are used to define the directions of Module IOs.
Note that they currently clone their source argument, including its bindings.
Thus, an error will be thrown if these are used on bound Data
Represents escaped percents
Utility for constructing hardware registers
Utility for constructing hardware registers
The width of a Reg
(inferred or not) is copied from the type template
val r0 = Reg(UInt()) // width is inferred val r1 = Reg(UInt(8.W)) // width is set to 8 val r2 = Reg(Vec(4, UInt())) // width is inferred val r3 = Reg(Vec(4, UInt(8.W))) // width of each element is set to 8 class MyBundle { val unknown = UInt() val known = UInt(8.W) } val r4 = Reg(new MyBundle) // Width of r4.unknown is inferred // Width of r4.known is set to 8
Utility for constructing hardware registers with an initialization value.
Utility for constructing hardware registers with an initialization value.
The register is set to the initialization value when the current implicit reset
is high
The two forms of RegInit
differ in how the type and width of the resulting Reg are
specified.
The single argument form uses the argument to specify both the type and reset value. For non-literal Bits, the width of the Reg will be inferred. For literal Bits and all non-Bits arguments, the type will be copied from the argument. See the following examples for more details:
1. Literal Bits initializer: width will be set to match
val r1 = RegInit(1.U) // width will be inferred to be 1 val r2 = RegInit(1.U(8.W)) // width is set to 8
2. Non-Literal Element initializer - width will be inferred
val x = Wire(UInt()) val y = Wire(UInt(8.W)) val r1 = RegInit(x) // width will be inferred val r2 = RegInit(y) // width is set to 8
3. Aggregate initializer - width will be set to match the aggregate
class MyBundle extends Bundle { val unknown = UInt() val known = UInt(8.W) } val w1 = Reg(new MyBundle) val w2 = RegInit(w1) // Width of w2.unknown is inferred // Width of w2.known is set to 8
The double argument form allows the type of the Reg and the default connection to be specified independently.
The width inference semantics for RegInit
with two arguments match those of Reg. The
first argument to RegInit
is the type template which defines the width of the Reg
in
exactly the same way as the only argument to Wire.
More explicitly, you can reason about RegInit
with multiple arguments as if it were defined
as:
def RegInit[T <: Data](t: T, init: T): T = { val x = Reg(t) x := init x }
Utility for constructing one-cycle delayed versions of signals
Utility for constructing one-cycle delayed versions of signals
The width of a RegNext
is not set based on the next
or init
connections for Element types. In the
following example, the width of bar
will not be set and will be inferred by the FIRRTL compiler.
val foo = Reg(UInt(4.W)) // width is 4 val bar = RegNext(foo) // width is unset
If you desire an explicit width, do not use RegNext
and instead use a register with a specified width:
val foo = Reg(UInt(4.W)) // width is 4 val bar = Reg(chiselTypeOf(foo)) // width is 4 bar := foo
Also note that a RegNext
of a Bundle will have it's width set for Aggregate types.
class MyBundle extends Bundle { val x = UInt(4.W) } val foo = Wire(new MyBundle) // the width of foo.x is 4 val bar = RegNext(foo) // the width of bar.x is 4
Utility for constructing hardware wires
Utility for constructing hardware wires
The width of a Wire
(inferred or not) is copied from the type template
val w0 = Wire(UInt()) // width is inferred val w1 = Wire(UInt(8.W)) // width is set to 8 val w2 = Wire(Vec(4, UInt())) // width is inferred val w3 = Wire(Vec(4, UInt(8.W))) // width of each element is set to 8 class MyBundle { val unknown = UInt() val known = UInt(8.W) } val w4 = Wire(new MyBundle) // Width of w4.unknown is inferred // Width of w4.known is set to 8
Utility for constructing hardware wires with a default connection
Utility for constructing hardware wires with a default connection
The two forms of WireDefault
differ in how the type and width of the resulting Wire are
specified.
The single argument form uses the argument to specify both the type and default connection. For non-literal Bits, the width of the Wire will be inferred. For literal Bits and all non-Bits arguments, the type will be copied from the argument. See the following examples for more details:
1. Literal Bits initializer: width will be set to match
val w1 = WireDefault(1.U) // width will be inferred to be 1 val w2 = WireDefault(1.U(8.W)) // width is set to 8
2. Non-Literal Element initializer - width will be inferred
val x = Wire(UInt()) val y = Wire(UInt(8.W)) val w1 = WireDefault(x) // width will be inferred val w2 = WireDefault(y) // width will be inferred
3. Aggregate initializer - width will be set to match the aggregate
class MyBundle { val unknown = UInt() val known = UInt(8.W) } val w1 = Wire(new MyBundle) val w2 = WireDefault(w1) // Width of w2.unknown is inferred // Width of w2.known is set to 8
The double argument form allows the type of the Wire and the default connection to be specified independently.
The width inference semantics for WireDefault
with two arguments match those of Wire. The
first argument to WireDefault
is the type template which defines the width of the Wire
in
exactly the same way as the only argument to Wire.
More explicitly, you can reason about WireDefault
with multiple arguments as if it were defined
as:
def WireDefault[T <: Data](t: T, init: T): T = { val x = Wire(t) x := init x }
The Default
in WireDefault
refers to a default
connection. This is in contrast to
RegInit where the Init
refers to a value on reset.
Returns the chisel type of a hardware object, allowing other hardware to be constructed from it.
These definitions exist to deal with those clients that relied on chisel3.core.
These definitions exist to deal with those clients that relied on chisel3.core. They are deprecated and will be removed in the future.
Marks that a signal should not be removed by Chisel and Firrtl optimization passes
Marks that a signal should not be removed by Chisel and Firrtl optimization passes
class MyModule extends Module { val io = IO(new Bundle { val a = Input(UInt(32.W)) val b = Output(UInt(32.W)) }) io.b := io.a val dead = io.a +% 1.U // normally dead would be pruned by DCE dontTouch(dead) // Marking it as such will preserve it }
Calling this on Data creates an annotation that Chisel emits to a separate annotations
file. This file must be passed to FIRRTL independently of the .fir
file. The execute methods
in chisel3.Driver will pass the annotations to FIRRTL automatically.
Package for experimental features, which may have their API changed, be removed, etc.
Package for experimental features, which may have their API changed, be removed, etc.
Because its contents won't necessarily have the same level of stability and support as non-experimental, you must explicitly import this package to use its contents.
Prints a message in simulation
Prints a message in simulation
See apply methods for use
This package contains the main chisel3 API.