Object

chisel3

RegNext

Related Doc: package chisel3

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object RegNext

Utility for constructing one-cycle delayed versions of signals

The width of a RegNext is not set based on the next or init connections for Element types. In the following example, the width of bar will not be set and will be inferred by the FIRRTL compiler.

val foo = Reg(UInt(4.W))         // width is 4
val bar = RegNext(foo)           // width is unset

If you desire an explicit width, do not use RegNext and instead use a register with a specified width:

val foo = Reg(UInt(4.W))         // width is 4
val bar = Reg(chiselTypeOf(foo)) // width is 4
bar := foo

Also note that a RegNext of a Bundle will have it's width set for Aggregate types.

class MyBundle extends Bundle {
  val x = UInt(4.W)
}
val foo = Wire(new MyBundle)     // the width of foo.x is 4
val bar = RegNext(foo)           // the width of bar.x is 4
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  1. final def !=(arg0: Any): Boolean

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  2. final def ##(): Int

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  3. final def ==(arg0: Any): Boolean

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  4. def apply[T <: Data](next: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T

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    Returns a register with an unset width connected to the signal next and with the reset value init.

  5. def apply[T <: Data](next: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T

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    Returns a register with an unset width connected to the signal next and with no reset value.

  6. final def asInstanceOf[T0]: T0

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  7. def clone(): AnyRef

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  10. def finalize(): Unit

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  11. final def getClass(): Class[_]

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  13. final def isInstanceOf[T0]: Boolean

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  14. final def ne(arg0: AnyRef): Boolean

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  15. final def notify(): Unit

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  16. final def notifyAll(): Unit

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  17. final def synchronized[T0](arg0: ⇒ T0): T0

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  19. final def wait(): Unit

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  20. final def wait(arg0: Long, arg1: Int): Unit

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