abstract class ExtModule extends BaseBlackBox
Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.
A variant of BlackBox, this has a more consistent naming scheme in allowing multiple top-level IO and does not drop the top prefix.
Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:
IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT")) ibufds ( .IB(ibufds_IB), .I(ibufds_I), .O(ibufds_O) );
To instantiate it, a BlackBox can be used like following:
import chisel3._ import chisel3.experimental._ // Example with Xilinx differential buffer IBUFDS class IBUFDS extends ExtModule(Map("DIFF_TERM" -> "TRUE", // Verilog parameters "IOSTANDARD" -> "DEFAULT" )) { val O = IO(Output(Clock())) val I = IO(Input(Clock())) val IB = IO(Input(Clock())) }
- Note
The parameters API is experimental and may change
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: Any): Boolean
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def
IO[T <: Data](iodef: T): T
This must wrap the datatype used to set the io field of any Module.
This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])
Items in [] are optional.
The granted iodef must be a chisel type and not be bound to hardware.
Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.
TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.
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- BaseModule
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def
_bindIoInPlace(iodef: Data): Unit
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.
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var
_closed: Boolean
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- protected
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- BaseModule
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def
_compatAutoWrapPorts(): Unit
Compatibility function.
Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.
Should NOT be used elsewhere. This API will NOT last.
TODO: remove this, perhaps by removing Bindings checks in compatibility mode.
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- BaseModule
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final
def
asInstanceOf[T0]: T0
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def
circuitName: String
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def
clone(): AnyRef
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def
desiredName: String
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The name of a module approximates the behavior of the Java Reflection method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:
- Anonymous modules will get an
"_Anon"
tag - Modules defined in functions will use their class name and not a numeric name- Definition Classes
- BaseModule
- Note
If you want a custom or parametric name, override this method.
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(that: Any): Boolean
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final
def
getClass(): Class[_]
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def
getIds: Seq[HasId]
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def
getModulePorts: Seq[Data]
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def
hashCode(): Int
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def
instanceName: String
Signal name (for simulation).
Signal name (for simulation).
- Definition Classes
- BaseModule → HasId → InstanceId
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final
def
isInstanceOf[T0]: Boolean
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final
lazy val
name: String
Legalized name of this module.
Legalized name of this module.
- Definition Classes
- BaseModule
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def
nameIds(rootClass: Class[_]): HashMap[HasId, String]
Called at the Module.apply(...) level after this Module has finished elaborating.
Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.
Helper method.
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final
def
ne(arg0: AnyRef): Boolean
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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- val params: Map[String, Param]
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def
parentModName: String
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def
parentPathName: String
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- HasId → InstanceId
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def
pathName: String
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- HasId → InstanceId
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def
portsContains(elem: Data): Boolean
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- protected
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- BaseModule
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def
portsSize: Int
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- BaseModule
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def
suggestName(name: ⇒ String): ExtModule.this.type
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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final
def
toAbsoluteTarget: IsModule
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
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final
def
toNamed: ModuleName
Returns a FIRRTL ModuleName that references this object
Returns a FIRRTL ModuleName that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
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def
toString(): String
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final
def
toTarget: ModuleTarget
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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final
def
wait(): Unit
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