abstract class MultiIOModule extends RawModule
Abstract base class for Modules, which behave much like Verilog modules. These may contain both logic and state which are written in the Module body (constructor). This abstract base class includes an implicit clock and reset.
- Note
Module instantiations must be wrapped in a Module() call.
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- MultiIOModule
- RawModule
- BaseModule
- HasId
- InstanceId
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Instance Constructors
- new MultiIOModule()(implicit moduleCompileOptions: CompileOptions)
Value Members
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final
def
!=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
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final
def
##(): Int
- Definition Classes
- AnyRef → Any
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final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
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def
IO[T <: Data](iodef: T): T
This must wrap the datatype used to set the io field of any Module.
This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])
Items in [] are optional.
The granted iodef must be a chisel type and not be bound to hardware.
Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.
TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.
- Attributes
- protected
- Definition Classes
- BaseModule
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def
_bindIoInPlace(iodef: Data): Unit
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.
- Attributes
- protected
- Definition Classes
- BaseModule
-
var
_closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
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def
_compatAutoWrapPorts(): Unit
Compatibility function.
Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.
Should NOT be used elsewhere. This API will NOT last.
TODO: remove this, perhaps by removing Bindings checks in compatibility mode.
- Definition Classes
- BaseModule
-
final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
-
def
circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- final val clock: Clock
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def
clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()
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val
compileOptions: CompileOptions
- Definition Classes
- RawModule
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def
computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]
Computes the name of this HasId, if one exists
Computes the name of this HasId, if one exists
- defaultPrefix
Optionally provide a default prefix for computing the name
- defaultSeed
Optionally provide default seed for computing the name
- returns
the name, if it can be computed
- Definition Classes
- HasId
-
def
desiredName: String
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The name of a module approximates the behavior of the Java Reflection method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:
- Anonymous modules will get an
"_Anon"
tag - Modules defined in functions will use their class name and not a numeric name- Definition Classes
- BaseModule
- Note
If you want a custom or parametric name, override this method.
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final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
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def
equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
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def
finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( classOf[java.lang.Throwable] )
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final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native()
-
def
getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
-
def
getIds: Seq[HasId]
- Attributes
- protected
- Definition Classes
- BaseModule
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def
getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
-
lazy val
getPorts: Seq[Port]
- Definition Classes
- RawModule
-
def
hasSeed: Boolean
- returns
Whether either autoName or suggestName has been called
- Definition Classes
- HasId
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def
hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
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def
instanceName: String
Signal name (for simulation).
Signal name (for simulation).
- Definition Classes
- BaseModule → HasId → InstanceId
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final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
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final
lazy val
name: String
Legalized name of this module.
Legalized name of this module.
- Definition Classes
- BaseModule
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def
nameIds(rootClass: Class[_]): HashMap[HasId, String]
Called at the Module.apply(...) level after this Module has finished elaborating.
Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.
Helper method.
- Attributes
- protected
- Definition Classes
- BaseModule
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final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
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final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
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final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
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def
parentModName: String
- Definition Classes
- HasId → InstanceId
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def
parentPathName: String
- Definition Classes
- HasId → InstanceId
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def
pathName: String
- Definition Classes
- HasId → InstanceId
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def
portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
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def
portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- final val reset: Reset
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def
suggestName(seed: ⇒ String): MultiIOModule.this.type
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.
- seed
The seed for the name of this component
- returns
this object
- Definition Classes
- HasId
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
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final
def
toAbsoluteTarget: IsModule
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
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final
def
toNamed: ModuleName
Returns a FIRRTL ModuleName that references this object
Returns a FIRRTL ModuleName that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
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def
toString(): String
- Definition Classes
- AnyRef → Any
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final
def
toTarget: ModuleTarget
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
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final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
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final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
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final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()