loadMemoryFromFile
Related Doc:
package experimental
Use this annotation generator to load a memory from a text file by using verilator and verilog's $readmemh or $readmemb.
Use this annotation generator to load a memory from a text file by using verilator and verilog's $readmemh or $readmemb. The treadle backend can also recognize this annotation and load memory at run-time.
This annotation triggers the LoadMemoryTransform which will take add the verilog directive to the relevant module by using the creating separate modules that are bound to the modules containing the memories to be loaded.
Consider a simple Module containing a memory
import chisel3._ class UsesMem(memoryDepth: Int, memoryType: Data) extends Module { val io = IO(new Bundle { val address = Input(UInt(memoryType.getWidth.W)) val value = Output(memoryType) }) val memory = Mem(memoryDepth, memoryType) io.value := memory(io.address) }
To load this memory from a file /workspace/workdir/mem1.hex.txt Just add an import and annotate the memory
import chisel3._ import chisel3.util.experimental.loadMemoryFromFile // <<-- new import here class UsesMem(memoryDepth: Int, memoryType: Data) extends Module { val io = IO(new Bundle { val address = Input(UInt(memoryType.getWidth.W)) val value = Output(memoryType) }) val memory = Mem(memoryDepth, memoryType) io.value := memory(io.address) loadMemoryFromFile(memory, "/workspace/workdir/mem1.hex.txt") // <<-- Note the annotation here }
A memory file should consist of ascii text in either hex or binary format Example (a file containing the decimal values 0, 7, 14, 21):
0 7 d 15
Binary file is similarly constructed.
See the LoadMemoryFromFileSpec.scala in the test suite for more examples