This is the annotation created when using loadMemoryFromFile, it records the memory, the load file and the format of the file.
This transform only is activated if verilog is being generated (determined by presence of the proper emit annotation) when activated it creates additional verilog files that contain modules bound to the modules that contain an initializable memory
This transform only is activated if verilog is being generated (determined by presence of the proper emit annotation) when activated it creates additional verilog files that contain modules bound to the modules that contain an initializable memory
Currently the only non-verilog based simulation that can support loading memory from a file is treadle but it does not need this transform to do that.
This is the annotation created when using loadMemoryFromFile, it records the memory, the load file and the format of the file.
memory to load
name of input file
use $readmemh or $readmemb, i.e. hex or binary text input, default is hex