trait LFSR extends PRNG
Trait that defines a Linear Feedback Shift Register (LFSR).
If the user specifies a seed, then a compile-time check is added that they are not initializing the LFSR to a state which will cause it to lock up. If the user does not set a seed, then the least significant bit of the state will be set or reset based on the choice of reduction operator.
- Alphabetic
- By Inheritance
- LFSR
- PRNG
- LegacyModule
- MultiIOModule
- RawModule
- BaseModule
- HasId
- InstanceId
- AnyRef
- Any
- Hide All
- Show All
- Public
- All
Abstract Value Members
Concrete Value Members
-
final
def
!=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
final
def
##(): Int
- Definition Classes
- AnyRef → Any
-
final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
def
IO[T <: Data](iodef: T): T
- Attributes
- protected
- Definition Classes
- BaseModule
-
def
_bindIoInPlace(iodef: Data): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
-
var
_closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
-
def
_compatAutoWrapPorts(): Unit
- Definition Classes
- BaseModule
-
def
_compatIoPortBound(): Boolean
- Attributes
- protected
- Definition Classes
- LegacyModule
-
final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
-
def
circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
-
final
val
clock: Clock
- Definition Classes
- MultiIOModule
-
def
clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()
-
val
compileOptions: CompileOptions
- Definition Classes
- RawModule
-
def
desiredName: String
- Definition Classes
- BaseModule
-
final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
def
equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
-
def
finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( classOf[java.lang.Throwable] )
-
final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native()
-
def
getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
-
def
getIds: Seq[HasId]
- Attributes
- protected
- Definition Classes
- BaseModule
-
def
getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
-
lazy val
getPorts: Seq[Port]
- Definition Classes
- RawModule
-
def
hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
-
def
instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
-
val
io: PRNGIO
- Definition Classes
- PRNG → LegacyModule
-
final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
-
final
lazy val
name: String
- Definition Classes
- BaseModule
-
def
nameIds(rootClass: Class[_]): HashMap[HasId, String]
- Attributes
- protected
- Definition Classes
- BaseModule
-
final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
final
def
nextState(s: Seq[Bool]): Seq[Bool]
The method that will be used to update the state of this PRNG
The method that will be used to update the state of this PRNG
- s
input state
- returns
the next state after
step
applications of PRNG.delta
- Definition Classes
- PRNG
-
final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
-
final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
-
var
override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- LegacyModule
-
var
override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- LegacyModule
-
def
parentModName: String
- Definition Classes
- HasId → InstanceId
-
def
parentPathName: String
- Definition Classes
- HasId → InstanceId
-
def
pathName: String
- Definition Classes
- HasId → InstanceId
-
def
portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
-
def
portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
-
final
val
reset: Reset
- Definition Classes
- MultiIOModule
-
def
resetValue: Vec[Bool]
Allow implementations to override the reset value, e.g., if some bits should be don't-cares.
-
val
seed: Option[BigInt]
- Definition Classes
- PRNG
-
def
suggestName(name: ⇒ String): LFSR.this.type
- Definition Classes
- HasId
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
-
final
def
toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
-
final
def
toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
-
def
toString(): String
- Definition Classes
- AnyRef → Any
-
final
def
toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
-
final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()
-
val
width: Int
- Definition Classes
- PRNG
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,FixedPoint
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.