final class HWTuple3[+A <: Data, +B <: Data, +C <: Data] extends Bundle
Data equivalent of Scala's scala.Tuple3
Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple3
in
chisel3.experimental.conversions
- Source
- package.scala
- Grouped
- Alphabetic
- By Inheritance
- HWTuple3
- Bundle
- Record
- Aggregate
- Data
- SourceInfoDoc
- NamedComponent
- HasId
- InstanceId
- AnyRef
- Any
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Value Members
-
final
def
!=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
final
def
##(): Int
- Definition Classes
- AnyRef → Any
-
final
def
:=(that: ⇒ Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
The "strong connect" operator.
The "strong connect" operator.
For chisel3._, this operator is mono-directioned; all sub-elements of
this
will be driven by sub-elements ofthat
.- Equivalent to
this :#= that
For Chisel._, this operator connections bi-directionally via emitting the FIRRTL.<=
- Equivalent to
this :<>= that
- that
the Data to connect from
- Definition Classes
- Data
- Equivalent to
-
final
def
<>(that: ⇒ Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
The "bulk connect operator", assigning elements in this Vec from elements in a Vec.
The "bulk connect operator", assigning elements in this Vec from elements in a Vec.
For chisel3._, uses the
chisel3.internal.BiConnect
algorithm; sub-elements of thatmay end up driving sub-elements of
this- Complicated semantics, hard to write quickly, will likely be deprecated in the future
For Chisel._, emits the FIRRTL.<- operator
- Equivalent to
this :<>= that
without the restrictions that bundle field names and vector sizes must match
- that
the Data to connect from
- Definition Classes
- Data
-
final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- val _1: A
- val _2: B
- val _3: C
-
def
_cloneTypeImpl: Bundle
Implementation of cloneType that is [optionally for Record] overridden by the compiler plugin
-
def
_elementsImpl: Iterable[(String, Any)]
This method is implemented by the compiler plugin
This method is implemented by the compiler plugin
- Attributes
- protected
- Definition Classes
- HWTuple3 → Bundle
- Note
For some reason, the Scala compiler errors on child classes if this method is made virtual. It appears that the way the plugin implements this method is insufficient for implementing virtual methods. It is probably better kept concrete for future refactoring.
-
def
_usingPlugin: Boolean
Indicates if a concrete Bundle class was compiled using the compiler plugin
-
final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
-
macro
def
asTypeOf[T <: Data](that: T): T
Does a reinterpret cast of the bits in this node into the format that provides.
Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.
x.asTypeOf(that) performs the inverse operation of x := that.toBits.
- Definition Classes
- Data
- Note
bit widths are NOT checked, may pad or drop bits from input
,that should have known widths
-
final macro
def
asUInt: UInt
Reinterpret cast to UInt.
Reinterpret cast to UInt.
- Definition Classes
- Data
- Note
value not guaranteed to be preserved: for example, a SInt of width 3 and value -1 (0b111) would become an UInt with value 7
,Aggregates are recursively packed with the first element appearing in the least-significant bits of the result.
-
def
autoSeed(name: String): HWTuple3.this.type
Takes the last seed suggested.
Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless this HasId is a module port (see overridden method in Data.scala).
If the final computed name conflicts with the final name of another signal, the final name may get uniquified by appending a digit at the end of the name.
Is a lower priority than suggestName, in that regardless of whether autoSeed was called, suggestName will always take precedence if it was called.
- returns
this object
- Definition Classes
- Data → HasId
- def binding: Option[Binding]
-
def
binding_=(target: Binding): Unit
- Attributes
- protected
- Definition Classes
- Data
-
def
circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
-
def
className: String
Name for Pretty Printing
-
def
clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native() @HotSpotIntrinsicCandidate()
-
def
cloneType: HWTuple3.this.type
Internal API; Chisel users should look at chisel3.chiselTypeOf(...).
-
def
do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- Definition Classes
- Data
- def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt
-
final
lazy val
elements: SeqMap[String, Data]
The collection of Data
The collection of Data
Elements defined earlier in the Bundle are higher order upon serialization. For example:
- Definition Classes
- Bundle → Record
class MyBundle extends Bundle { val foo = UInt(16.W) val bar = UInt(16.W) } // Note that foo is higher order because its defined earlier in the Bundle val bundle = Wire(new MyBundle) bundle.foo := 0x1234.U bundle.bar := 0x5678.U val uint = bundle.asUInt assert(uint === "h12345678".U) // This will pass
Example: -
final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
def
equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
-
final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
def
getElements: Seq[Data]
Returns a Seq of the immediate contents of this Aggregate, in order.
-
final
def
getWidth: Int
Returns the width, in bits, if currently known.
Returns the width, in bits, if currently known.
- Definition Classes
- Data
-
def
hasSeed: Boolean
- returns
Whether either autoName or suggestName has been called
- Definition Classes
- HasId
-
def
hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
-
def
ignoreSeq: Boolean
Overridden by IgnoreSeqInBundle to allow arbitrary Seqs of Chisel elements.
Overridden by IgnoreSeqInBundle to allow arbitrary Seqs of Chisel elements.
- Definition Classes
- Bundle
-
def
instanceName: String
- Definition Classes
- HasId → InstanceId
-
final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
-
def
isLit: Boolean
- Definition Classes
- Data
-
final
def
isWidthKnown: Boolean
Returns whether the width is currently known.
Returns whether the width is currently known.
- Definition Classes
- Data
-
def
litOption: Option[BigInt]
Return an Aggregate's literal value if it is a literal, None otherwise.
-
def
litValue: BigInt
Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
-
final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
def
parentModName: String
- Definition Classes
- HasId → InstanceId
-
def
parentPathName: String
- Definition Classes
- HasId → InstanceId
-
def
pathName: String
- Definition Classes
- HasId → InstanceId
-
def
suggestName(seed: ⇒ String): HWTuple3.this.type
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than
autoSeed
, in that regardless of whetherautoSeed
was called, suggestName will always take precedence.- seed
The seed for the name of this component
- returns
this object
- Definition Classes
- HasId
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
-
final
def
toAbsoluteTarget: ReferenceTarget
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
- Definition Classes
- NamedComponent → InstanceId
-
final
def
toNamed: ComponentName
Returns a FIRRTL ComponentName that references this object
Returns a FIRRTL ComponentName that references this object
- Definition Classes
- NamedComponent → InstanceId
- Note
Should not be called until circuit elaboration is complete
-
def
toPrintable: Printable
Default "pretty-print" implementation Analogous to printing a Map Results in "
Bundle(elt0.name -> elt0.value, ...)
" -
def
toString(): String
The collection of chisel3.Data
The collection of chisel3.Data
This underlying datastructure is a ListMap because the elements must remain ordered for serialization/deserialization. Elements added later are higher order when serialized (this is similar to
Vec
). For example:// Assume we have some type MyRecord that creates a Record from the ListMap val record = MyRecord(ListMap("fizz" -> UInt(16.W), "buzz" -> UInt(16.W))) // "buzz" is higher order because it was added later than "fizz" record("fizz") := "hdead".U record("buzz") := "hbeef".U val uint = record.asUInt assert(uint === "hbeefdead".U) // This will pass
- Definition Classes
- Record → AnyRef → Any
-
final
def
toTarget: ReferenceTarget
Returns a FIRRTL ReferenceTarget that references this object
Returns a FIRRTL ReferenceTarget that references this object
- Definition Classes
- NamedComponent → InstanceId
- Note
Should not be called until circuit elaboration is complete
-
final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()
-
final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
final
def
widthOption: Option[Int]
Returns Some(width) if the width is known, else None.
Returns Some(width) if the width is known, else None.
- Definition Classes
- Data
Inherited from Bundle
Inherited from Record
Inherited from Aggregate
Inherited from Data
Inherited from SourceInfoDoc
Inherited from NamedComponent
Inherited from HasId
Inherited from InstanceId
Inherited from AnyRef
Inherited from Any
connection
Ungrouped
SourceInfoTransformMacro
These internal methods are not part of the public-facing API!
The equivalent public-facing methods do not have the do_
prefix or have the same name. Use and look at the
documentation for those. If you want left shift, use <<
, not do_<<
. If you want conversion to a
Seq of Bools look at the asBools
above, not the one below. Users can safely ignore
every method in this group!
🐉🐉🐉 Here be dragons... 🐉🐉🐉
These do_X
methods are used to enable both implicit passing of SourceInfo and chisel3.CompileOptions
while also supporting chained apply methods. In effect all "normal" methods that you, as a user, will use in your
designs, are converted to their "hidden", do_*
, via macro transformations. Without using macros here, only one
of the above wanted behaviors is allowed (implicit passing and chained applies)---the compiler interprets a
chained apply as an explicit 'implicit' argument and will throw type errors.
The "normal", public-facing methods then take no SourceInfo. However, a macro transforms this public-facing method
into a call to an internal, hidden do_*
that takes an explicit SourceInfo by inserting an
implicitly[SourceInfo]
as the explicit argument.
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,FixedPoint
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.