o

chisel3.util

ShiftRegisters

object ShiftRegisters

Source
Reg.scala
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  1. final def !=(arg0: Any): Boolean
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  4. macro def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): Seq[T]

    Returns delayed input signal registers with reset initialization from 1 to n.

    Returns delayed input signal registers with reset initialization from 1 to n.

    in

    input to delay

    n

    number of cycles to delay

    resetData

    reset value for each register in the shift

    en

    enable the shift

  5. macro def apply[T <: Data](in: T, n: Int): Seq[T]

    Returns a sequence of delayed input signal registers from 1 to n.

    Returns a sequence of delayed input signal registers from 1 to n.

    Enable is assumed to be true.

    in

    input to delay

    n

    number of cycles to delay

  6. macro def apply[T <: Data](in: T, n: Int, en: Bool): Seq[T]

    Returns a sequence of delayed input signal registers from 1 to n.

    Returns a sequence of delayed input signal registers from 1 to n.

    in

    input to delay

    n

    number of cycles to delay

    en

    enable the shift

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  9. def do_apply[T <: Data](in: T, n: Int, resetData: T, en: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Seq[T]

  10. def do_apply[T <: Data](in: T, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Seq[T]

  11. def do_apply[T <: Data](in: T, n: Int, en: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Seq[T]

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