Packages

•  package root

  This is the documentation for Chisel.

  This is the documentation for Chisel.

  Package structure

  The chisel3 package presents the public API of Chisel. It contains the concrete core types UInt, SInt, Bool, FixedPoint, Clock, and Reg, the abstract types Bits, Aggregate, and Data, and the aggregate types Bundle and Vec.

  The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.

  Utility objects and methods are found in the util package.

  The testers package defines the basic interface for chisel testers.

  Definition Classes

  root

•  package chisel3

  Definition Classes

  root

•  package util

  The util package provides extensions to core chisel for common hardware components and utility functions

  The util package provides extensions to core chisel for common hardware components and utility functions

  Definition Classes

  chisel3

•  class Pipe[T <: Data] extends Module

  Pipeline module generator parameterized by data type and latency.

  Pipeline module generator parameterized by data type and latency.

  This defines a module with one input, enq, and one output, deq. The input and output are Valid interfaces that wrap some Chisel type, e.g., a UInt or a Bundle. This generator will then chain together a number of pipeline stages that all advance when the input Valid enq fires. The output deq Valid will fire only when valid data has made it all the way through the pipeline.

  As an example, to construct a 4-stage pipe of 8-bit UInts and connect it to a producer and consumer, you can use the following:

  val foo = Module(new Pipe(UInt(8.W)), 4)
  pipe.io.enq := producer.io
  consumer.io := pipe.io.deq

  If you already have the Valid input or the components of a Valid interface, it may be simpler to use the Pipe factory companion object. This, which Pipe internally utilizes, will automatically connect the input for you.

  Definition Classes

  util

  See also

  Pipe factory for an alternative API

  Valid interface

  Queue and the Queue factory for actual queues

  The ShiftRegister factory to generate a pipe without a Valid interface

• PipeIO

chisel3.util.Pipe

PipeIO