class ChiselStage extends Stage
- Alphabetic
- By Inheritance
- ChiselStage
- Stage
- Phase
- DependencyAPI
- TransformLike
- LazyLogging
- AnyRef
- Any
- Hide All
- Show All
- Public
- Protected
Instance Constructors
- new ChiselStage()
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- final def emitChirrtl(gen: => RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String
Convert a Chisel module to a CHIRRTL string
Convert a Chisel module to a CHIRRTL string
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel
- annotations
additional annotations to pass to Chisel
- returns
a string containing the Verilog output
- final def emitFirrtl(gen: => RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String
Convert a Chisel module to a FIRRTL string
Convert a Chisel module to a FIRRTL string
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel
- annotations
additional annotations to pass to Chisel
- returns
a string containing the FIRRTL output
- final def emitSystemVerilog(gen: => RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String
Convert a Chisel module to SystemVerilog
Convert a Chisel module to SystemVerilog
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel
- annotations
additional annotations to pass to Chisel
- returns
a string containing the SystemVerilog output
- final def emitVerilog(gen: => RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String
Convert a Chisel module to Verilog
Convert a Chisel module to Verilog
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel
- annotations
additional annotations to pass to Chisel
- returns
a string containing the Verilog output
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef → Any
- final def execute(args: Array[String], annotations: AnnotationSeq): AnnotationSeq
- Definition Classes
- Stage
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def getLogger: Logger
- Definition Classes
- LazyLogging
- def hashCode(): Int
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def invalidates(a: Phase): Boolean
- Definition Classes
- ChiselStage → DependencyAPI
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val logger: Logger
- Attributes
- protected
- Definition Classes
- LazyLogging
- lazy val name: String
- Definition Classes
- Phase → TransformLike
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def optionalPrerequisiteOf: Seq[Dependency[FirrtlStage]]
- Definition Classes
- ChiselStage → DependencyAPI
- def optionalPrerequisites: Seq[Nothing]
- Definition Classes
- ChiselStage → DependencyAPI
- final lazy val phaseManager: ChiselPhase
- def prerequisites: Seq[Nothing]
- Definition Classes
- ChiselStage → DependencyAPI
- def run(annotations: AnnotationSeq): AnnotationSeq
- Definition Classes
- ChiselStage → Stage
- val shell: Shell
- Definition Classes
- ChiselStage → Stage
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val targets: Seq[PhaseDependency]
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def transform(annotations: AnnotationSeq): AnnotationSeq
- Definition Classes
- Stage → TransformLike
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
Deprecated Value Members
- def dependents: Seq[Dependency[Phase]]
- Definition Classes
- DependencyAPI
- Annotations
- @deprecated
- Deprecated
(Since version FIRRTL 1.3) Due to confusion, 'dependents' is being renamed to 'optionalPrerequisiteOf'. Override the latter instead.
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,FixedPoint,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.