abstract class Module extends RawModule
Abstract base class for Modules, which behave much like Verilog modules. These may contain both logic and state which are written in the Module body (constructor). This abstract base class includes an implicit clock and reset.
- Source
- Module.scala
- Note
Module instantiations must be wrapped in a Module() call.
- Alphabetic
- By Inheritance
- Module
- RawModule
- BaseModule
- IsInstantiable
- HasId
- InstanceId
- AnyRef
- Any
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- Public
- Protected
Instance Constructors
- new Module()(implicit moduleCompileOptions: CompileOptions)
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: T): T
This must wrap the datatype used to set the io field of any Module.
This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])
Items in [] are optional.
The granted iodef must be a chisel type and not be bound to hardware.
Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.
TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.
- Attributes
- protected
- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data): Unit
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it.
Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _compatAutoWrapPorts(): Unit
Compatibility function.
Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.
Should NOT be used elsewhere. This API will NOT last.
TODO: remove this, perhaps by removing Bindings checks in compatibility mode.
- Definition Classes
- BaseModule
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- final val clock: Clock
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- val compileOptions: CompileOptions
- Definition Classes
- RawModule
- def desiredName: String
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The desired name of this module (which will be used in generated FIRRTL IR or Verilog).
The name of a module approximates the behavior of the Java Reflection method https://docs.oracle.com/javase/8/docs/api/java/lang/Class.html#getSimpleName-- with some modifications:
- Anonymous modules will get an
"_Anon"tag - Modules defined in functions will use their class name and not a numeric name- Definition Classes
- BaseModule
- Note
If you want a custom or parametric name, override this method.
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def hasSeed: Boolean
- returns
Whether either autoName or suggestName has been called
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def instanceName: String
Signal name (for simulation).
Signal name (for simulation).
- Definition Classes
- BaseModule → HasId → InstanceId
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- final lazy val name: String
Legalized name of this module.
Legalized name of this module.
- Definition Classes
- BaseModule
- def nameIds(rootClass: Class[_]): HashMap[HasId, String]
Called at the Module.apply(...) level after this Module has finished elaborating.
Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.
Helper method.
- Attributes
- protected
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- final val reset: Reset
- def suggestName(seed: => String): Module.this.type
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.
- seed
The seed for the name of this component
- returns
this object
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- final def toAbsoluteTarget: IsModule
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
- final def toNamed: ModuleName
Returns a FIRRTL ModuleName that references this object
Returns a FIRRTL ModuleName that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
Returns a FIRRTL ModuleTarget that references this object
Returns a FIRRTL ModuleTarget that references this object
- Definition Classes
- BaseModule → InstanceId
- Note
Should not be called until circuit elaboration is complete
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- lazy val getPorts: Seq[Port]
- Definition Classes
- RawModule
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use DataMirror.modulePorts instead. this API will be removed in Chisel 3.6
- def override_clock: Option[Clock]
- Attributes
- protected
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,FixedPoint,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.