object ShiftRegisters
- Source
- Reg.scala
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- def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): Seq[T]
Returns delayed input signal registers with reset initialization from 1 to n.
Returns delayed input signal registers with reset initialization from 1 to n.
- in
input to delay
- n
number of cycles to delay
- resetData
reset value for each register in the shift
- en
enable the shift
- def apply[T <: Data](in: T, n: Int, en: Bool = true.B): Seq[T]
Returns a sequence of delayed input signal registers from 1 to n.
Returns a sequence of delayed input signal registers from 1 to n.
- in
input to delay
- n
number of cycles to delay
- en
enable the shift
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,FixedPoint,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.