object ChiselStage
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- def convert(chirrtl: Circuit): Circuit
Return a firrtl.ir.Circuit for a chisel3.internal.firrtl.Circuit(aka chirrtl)
Return a firrtl.ir.Circuit for a chisel3.internal.firrtl.Circuit(aka chirrtl)
- chirrtl
chisel3.internal.firrtl.Circuit which need to be converted to firrtl.ir.Circuit
- def convert(gen: => RawModule): Circuit
Return a CHIRRTL circuit for a Chisel module
Return a CHIRRTL circuit for a Chisel module
- gen
a call-by-name Chisel module
- def elaborate(gen: => RawModule): Circuit
Return a Chisel circuit for a Chisel module
Return a Chisel circuit for a Chisel module
- gen
a call-by-name Chisel module
- def emitChirrtl(gen: => RawModule): String
Return a CHIRRTL string for a Chisel module
Return a CHIRRTL string for a Chisel module
- gen
a call-by-name Chisel module
- def emitFirrtl(gen: => RawModule): String
Return a FIRRTL string for a Chisel module
Return a FIRRTL string for a Chisel module
- gen
a call-by-name Chisel module
- def emitSystemVerilog(gen: => RawModule): String
Return a SystemVerilog string for a Chisel module
Return a SystemVerilog string for a Chisel module
- gen
a call-by-name Chisel module
- def emitVerilog(gen: => RawModule): String
Return a Verilog string for a Chisel module
Return a Verilog string for a Chisel module
- gen
a call-by-name Chisel module
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,FixedPoint,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.