object group
Marks that a module to be ignored in Dedup Transform in Firrtl pass
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.6) this feature will not be supported as part of the migration to the MLIR-based FIRRTL Compiler (MFC). For more information about this migration, please see the Chisel ROADMAP.md.
- Source
- group.scala
class MyModule extends Module { val io = IO(new Bundle{ val a = Input(Bool()) val b = Output(Bool()) }) val reg1 = RegInit(0.U) reg1 := io.a val reg2 = RegNext(reg1) io.b := reg2 group(Seq(reg1, reg2), "DosRegisters", "doubleReg") }
- Note
Intermediate wires will get pulled into the new instance, but intermediate registers will not because they are also connected to their module's clock port. This means that if you want a register to be included in a group, it must be explicitly referred to in the input list.
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- def apply[T <: Data](components: Seq[T], newModule: String, newInstance: String, outputSuffix: Option[String] = None, inputSuffix: Option[String] = None)(implicit compileOptions: CompileOptions): Unit
Marks a set of components (and their interconnected components) to be included in a new instance hierarchy.
Marks a set of components (and their interconnected components) to be included in a new instance hierarchy.
- T
Parent type of input components
- components
components in this group
- newModule
suggested name of the new module
- newInstance
suggested name of the instance of the new module
- outputSuffix
suggested suffix of any output ports of the new module
- inputSuffix
suggested suffix of any input ports of the new module
- compileOptions
necessary for backwards compatibility
- Note
Intermediate wires will get pulled into the new instance, but intermediate registers will not because they are also connected to their module's clock port. This means that if you want a register to be included in a group, it must be explicitly referred to in the input list.
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,FixedPoint,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.