Memory
Related Docs:
object Memory
| package firrtl_interpreter
source level information
the name of this memory
type of each memory element
number of elements
how many cycles before write happens
how many cycles before read happens
a list of named reader ports
a list of named writer ports
list of named read/write ports
behavior
wrap underlying data storage array so indexing is automatically constrained at depth
implements a read port with memory defined latency
implements a read port with memory defined latency
name of this reader
the number of cycles between port and memory
implements a write port with memory defined latency
implements a write port with memory defined latency
name of this writer
the number of cycles between port and memory
used to inform this memory that a cycle has passed
type of each memory element
number of elements
source level information
the name of this memory
how many cycles before read happens
behavior
list of named read/write ports
a list of named reader ports
delegate the concrete value to a port various actions may ensue depending on the
delegate the concrete value to a port various actions may ensue depending on the
full ram.port.field specifier
current value
how many cycles before write happens
a list of named writer ports
(Since version ) see corresponding Javadoc for more information.
provides a black box implementation of a circuit memory presenting read, write and read/write interfaces
Assumptions: Zero read_latency latches data straight to memory(address): IGNORES enable