class Memory extends SimpleLogger

provides a black box implementation of a circuit memory presenting read, write and read/write interfaces

Assumptions: Zero read_latency latches data straight to memory(address): IGNORES enable

Source
Memory.scala
Linear Supertypes
SimpleLogger, AnyRef, Any
Type Hierarchy
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Inherited
  1. Memory
  2. SimpleLogger
  3. AnyRef
  4. Any
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Visibility
  1. Public
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Instance Constructors

  1. new Memory(info: Info, name: String, dataType: Type, depth: Int, writeLatency: Int, readLatency: Int, readers: Seq[String], writers: Seq[String], readWriters: Seq[String], readUnderWrite: String)

    info

    source level information

    name

    the name of this memory

    dataType

    type of each memory element

    depth

    number of elements

    writeLatency

    how many cycles before write happens

    readLatency

    how many cycles before read happens

    readers

    a list of named reader ports

    writers

    a list of named writer ports

    readWriters

    list of named read/write ports

    readUnderWrite

    behavior

Type Members

  1. class DataStore extends AnyRef

    wrap underlying data storage array so indexing is automatically constrained at depth

  2. abstract class MemoryPort extends AnyRef
  3. trait PipeLineElement extends AnyRef
  4. case class ReadPort (portName: String, latency: Int) extends MemoryPort with Product with Serializable

    implements a read port with memory defined latency

    implements a read port with memory defined latency

    portName

    name of this reader

    latency

    the number of cycles between port and memory

  5. case class ReadWritePort (portName: String) extends MemoryPort with Product with Serializable
  6. case class WritePort (portName: String, latency: Int) extends MemoryPort with Product with Serializable

    implements a write port with memory defined latency

    implements a write port with memory defined latency

    portName

    name of this writer

    latency

    the number of cycles between port and memory

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. val addressWidth: Int
  5. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  6. val bigDepth: BigInt
  7. def clone(): AnyRef
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  8. def cycle(): Unit

    used to inform this memory that a cycle has passed

  9. val dataStore: DataStore
  10. val dataType: Type
  11. val dataWidth: Int
  12. val depth: Int
  13. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  14. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  15. def finalize(): Unit
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  16. def forceWrite(offset: Int, value: BigInt): Unit
  17. def getAllFieldDependencies: Seq[String]
  18. def getAllOutputFields: Seq[(String, Seq[String])]
  19. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
  20. def getValue(key: String): Concrete
  21. def hashCode(): Int
    Definition Classes
    AnyRef → Any
  22. val info: Info
  23. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  24. def log(msg: ⇒ String): Unit
    Definition Classes
    SimpleLogger
  25. val maxMemoryInDefaultDisplay: Int
  26. var moduloIndex: Boolean
  27. val name: String
  28. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  29. final def notify(): Unit
    Definition Classes
    AnyRef
  30. final def notifyAll(): Unit
    Definition Classes
    AnyRef
  31. val ports: Map[String, MemoryPort]
  32. val readLatency: Int
  33. val readPorts: Array[ReadPort]
  34. val readUnderWrite: String
  35. val readWritePorts: Array[ReadWritePort]
  36. val readWriters: Seq[String]
  37. val readers: Seq[String]
  38. def setValue(key: String, concreteValue: Concrete): Unit

    delegate the concrete value to a port various actions may ensue depending on the

    delegate the concrete value to a port various actions may ensue depending on the

    key

    full ram.port.field specifier

    concreteValue

    current value

  39. def setVerbose(value: Boolean = true): Unit
    Definition Classes
    SimpleLogger
  40. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  41. def toString(): String
    Definition Classes
    Memory → AnyRef → Any
  42. val verbose: Boolean
    Definition Classes
    SimpleLogger
  43. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  44. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  45. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  46. val writeLatency: Int
  47. val writePorts: Array[WritePort]
  48. val writers: Seq[String]

Inherited from SimpleLogger

Inherited from AnyRef

Inherited from Any

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