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–
deprecated
firrtl
(object)
Addw
(object)
(class)
AnnotationSeq
(object)
BIGENDER
(object)
bitWidth
(object)
castRhs
(case class)
CDefMemory
(case class)
CDefMPort
(object)
ChirrtlForm
(class)
ChirrtlToHighFirrtl
(class)
CircuitForm
(object)
(case class)
CircuitState
(case class)
CommonOptions
(trait)
Compiler
(object)
CompilerUtils
(trait)
ComposableOptions
(object)
connectFields
(trait)
Constraint
(class)
CoreTransform
(object)
Driver
(object)
Dshlw
(case class)
EmitAllModulesAnnotation
(trait)
EmitAnnotation
(case class)
EmitCircuitAnnotation
(trait)
EmittedAnnotation
(class)
EmittedCircuit
(trait)
EmittedCircuitAnnotation
(class)
EmittedComponent
(case class)
EmittedFirrtlCircuit
(case class)
EmittedFirrtlCircuitAnnotation
(case class)
EmittedFirrtlModule
(case class)
EmittedFirrtlModuleAnnotation
(class)
EmittedModule
(trait)
EmittedModuleAnnotation
(case class)
EmittedVerilogCircuit
(case class)
EmittedVerilogCircuitAnnotation
(case class)
EmittedVerilogModule
(case class)
EmittedVerilogModuleAnnotation
(trait)
Emitter
(case class)
EmitterException
(object)
EmptyExpression
(class)
ExecutionOptionsManager
(object)
ExpKind
(case class)
ExpWidth
(object)
FEMALE
(object)
FileUtils
(class)
FirrtlEmitter
(object)
(class)
FIRRTLException
(case class)
FirrtlExecutionFailure
(case class)
FirrtlExecutionOptions
(trait)
FirrtlExecutionResult
(object)
(class)
FirrtlExecutionSuccess
(object)
flattenType
(object)
fromBits
(trait)
Gender
(object)
getWidth
(trait)
HasCommonOptions
(trait)
HasFirrtlOptions
(class)
HasParser
(class)
HighFirrtlCompiler
(class)
HighFirrtlEmitter
(class)
HighFirrtlToMiddleFirrtl
(object)
HighForm
(object)
InstanceKind
(case class)
InvalidEscapeCharException
(case class)
InvalidStringLitException
(class)
IRToWorkingIR
(trait)
Kind
(class)
LexerHelper
(class)
LowFirrtlCompiler
(class)
LowFirrtlEmitter
(class)
LowFirrtlOptimization
(object)
LowForm
(object)
MALE
(object)
Mappers
(case class)
MaxWidth
(object)
MemKind
(object)
(class)
MemoizedHash
(class)
MiddleFirrtlCompiler
(class)
MiddleFirrtlEmitter
(class)
MiddleFirrtlToLowFirrtl
(object)
MidForm
(object)
MInfer
(class)
MinimumLowFirrtlOptimization
(class)
MinimumVerilogCompiler
(case class)
MinusWidth
(case class)
MinWidth
(class)
ModuleGraph
(class)
MPortDir
(object)
MRead
(object)
MReadWrite
(object)
MWrite
(object)
(class)
Namespace
(object)
NodeKind
(case class)
OneFilePerModule
(class)
OutputConfig
(case class)
ParameterNotSpecifiedException
(case class)
ParameterRedefinedException
(object)
Parser
(class)
ParserException
(case class)
PlusWidth
(object)
PoisonKind
(object)
PortKind
(object)
PrimOps
(object)
RegKind
(object)
(class)
RenameMap
(class)
ResolveAndCheck
(object)
seqCat
(class)
SeqTransform
(trait)
SeqTransformBased
(object)
Shlw
(case class)
SingleFile
(object)
Subw
(case class)
SyntaxErrorsException
(class)
SystemVerilogCompiler
(case class)
TargetDirAnnotation
(object)
toBits
(class)
Transform
(object)
UnknownForm
(object)
UNKNOWNGENDER
(object)
Utils
(case class)
VarWidth
(class)
VerilogCompiler
(class)
VerilogEmitter
(class)
Visitor
(case class)
VRandom
(object)
(case class)
WDefInstance
(case class)
WDefInstanceConnector
(object)
(class)
WGeq
(object)
WInvalid
(object)
WireKind
(object)
(class)
WrappedExpression
(object)
(class)
WrappedType
(object)
(class)
WrappedWidth
(object)
(case class)
WRef
(case class)
WSubAccess
(object)
(case class)
WSubField
(case class)
WSubIndex
(object)
WVoid
firrtl.altIR
(class)
AssignableGraphNode
(class)
ConnectGraphNode
(class)
DefInstanceGraphNode
(class)
DefWireGraphNode
(class)
ExpressionGraphNode
(class)
FirrtlGraphNode
(object)
getGraphNode
(class)
IsInvalidGraphNode
(class)
NamedGraphNode
(class)
PortGraphNode
(class)
ReferenceGraphNode
(class)
StatementGraphNode
(class)
SubFieldGraphNode
(class)
SubIndexGraphNode
firrtl.analyses
(class)
GetNamespace
(object)
(class)
InstanceGraph
(case class)
ModuleNamespaceAnnotation
(object)
(class)
NodeCount
firrtl.annotations
(object)
(trait)
Annotation
(case class)
AnnotationClassNotFoundException
(case class)
AnnotationException
(case class)
AnnotationFileNotFoundException
(object)
AnnotationUtils
(object)
AnnotationYamlProtocol
(case class)
CircuitName
(case class)
ComponentName
(case class)
DeletedAnnotation
(case class)
InvalidAnnotationFileException
(case class)
InvalidAnnotationJSONException
(object)
JsonProtocol
(case class)
LegacyAnnotation
(case class)
ModuleName
(trait)
Named
(trait)
NoTargetAnnotation
(trait)
SingleStringAnnotation
(trait)
SingleTargetAnnotation
firrtl.antlr
(class)
FIRRTLBaseVisitor
(class)
FIRRTLLexer
(class)
FIRRTLParser
(trait)
FIRRTLVisitor
firrtl.graph
(class)
CyclicException
(object)
(class)
DiGraph
(object)
(class)
EulerTour
(class)
MutableDiGraph
(class)
PathNotFoundException
firrtl.ir
(class)
AggregateType
(case class)
AnalogType
(case class)
Attach
(case class)
Block
(case class)
BundleType
(case class)
Circuit
(object)
ClockType
(case class)
Conditionally
(case class)
Connect
(object)
Default
(case class)
DefInstance
(case class)
DefMemory
(class)
DefModule
(case class)
DefNode
(case class)
DefRegister
(case class)
DefWire
(class)
Direction
(case class)
DoPrim
(case class)
DoubleParam
(object)
EmptyStmt
(class)
Expression
(case class)
ExtModule
(case class)
Field
(case class)
FileInfo
(class)
FirrtlNode
(case class)
FixedLiteral
(case class)
FixedType
(object)
Flip
(object)
(class)
GroundType
(trait)
HasInfo
(trait)
HasName
(class)
Info
(object)
Input
(case class)
IntParam
(object)
(class)
IntWidth
(trait)
IsDeclaration
(case class)
IsInvalid
(class)
Literal
(case class)
Module
(object)
(case class)
MultiInfo
(case class)
Mux
(object)
NoInfo
(class)
Orientation
(object)
Output
(class)
Param
(case class)
PartialConnect
(case class)
Port
(class)
PrimOp
(case class)
Print
(case class)
RawStringParam
(case class)
Reference
(case class)
SIntLiteral
(case class)
SIntType
(class)
Statement
(case class)
Stop
(object)
(case class)
StringLit
(case class)
StringParam
(case class)
SubAccess
(case class)
SubField
(case class)
SubIndex
(class)
Type
(case class)
UIntLiteral
(case class)
UIntType
(object)
UnknownType
(object)
UnknownWidth
(case class)
ValidIf
(case class)
VectorType
(class)
Width
firrtl.passes
(object)
CheckChirrtl
(object)
CheckGenders
(object)
CheckHighForm
(object)
CheckInitialization
(object)
CheckTypes
(object)
CheckWidths
(object)
CInferMDir
(object)
CInferTypes
(object)
CommonSubexpressionElimination
(object)
ConvertFixedToSInt
(object)
createMask
(case class)
DataRef
(object)
DeadCodeElimination
(class)
Errors
(object)
ExpandConnects
(object)
ExpandWhens
(object)
InferTypes
(object)
InferWidths
(case class)
InlineAnnotation
(class)
InlineInstances
(object)
Legalize
(object)
LowerTypes
(object)
MemPortUtils
(case class)
MPort
(case class)
MPorts
(object)
PadWidths
(trait)
Pass
(class)
PassException
(class)
PassExceptions
(object)
PullMuxes
(object)
RemoveAccesses
(object)
RemoveCHIRRTL
(object)
RemoveEmpty
(object)
RemoveValidIf
(object)
ReplaceAccesses
(object)
ResolveGenders
(object)
ResolveKinds
(object)
SplitExpressions
(object)
toBitMask
(object)
ToWorkingIR
(object)
Uniquify
(object)
VerilogModulusCleanup
(object)
VerilogPrep
(object)
VerilogRename
(object)
ZeroWidth
firrtl.passes.clocklist
(class)
ClockList
(object)
(case class)
ClockListAnnotation
(class)
ClockListTransform
(object)
ClockListUtils
(object)
RemoveAllButClocks
firrtl.passes.memlib
(object)
AnalysisUtils
(case class)
Config
(class)
ConfWriter
(class)
CreateMemoryAnnotations
(object)
CustomYAMLProtocol
(case class)
DefAnnotatedMemory
(class)
InferReadWrite
(object)
InferReadWriteAnnotation
(object)
InferReadWritePass
(object)
InputConfigFileName
(object)
MemTransformUtils
(case class)
NoDedupMemAnnotation
(object)
OutputConfigFileName
(object)
PassCircuitName
(object)
PassConfigUtil
(object)
PassModuleName
(trait)
PassOption
(case class)
Pin
(case class)
PinAnnotation
(object)
RenameAnnotatedMemoryPorts
(class)
ReplaceMemMacros
(class)
ReplSeqMem
(object)
(case class)
ReplSeqMemAnnotation
(object)
ResolveMaskGranularity
(class)
ResolveMemoryReference
(class)
SimpleMidTransform
(class)
SimpleTransform
(case class)
Source
(object)
ToMemIR
(case class)
Top
(object)
VerilogMemDelays
(class)
YamlFileReader
(class)
YamlFileWriter
firrtl.passes.wiring
(object)
DecInput
(trait)
DecKind
(object)
DecOutput
(object)
DecWire
(case class)
Lineage
(case class)
Modifications
(case class)
SinkAnnotation
(case class)
SourceAnnotation
(class)
Wiring
(case class)
WiringException
(case class)
WiringInfo
(case class)
WiringNames
(class)
WiringTransform
(object)
WiringUtils
firrtl.transforms
(trait)
BlackBoxHelperAnno
(case class)
BlackBoxInlineAnno
(case class)
BlackBoxResourceAnno
(object)
(class)
BlackBoxSourceHelper
(case class)
BlackBoxTargetDirAnno
(object)
(class)
CheckCombLoops
(case class)
CombinationalPath
(object)
(class)
ConstantPropagation
(class)
DeadCodeElimination
(object)
(class)
DedupModules
(object)
DontCheckCombLoopsAnnotation
(object)
(case class)
DontTouchAnnotation
(class)
Flatten
(case class)
FlattenAnnotation
(class)
GroupAndDedup
(case class)
GroupAnnotation
(class)
GroupComponents
(object)
NoDCEAnnotation
(case class)
NoDedupAnnotation
(case class)
OptimizableExtModuleAnnotation
(class)
RemoveReset
(class)
RemoveWires
(class)
RenameModules
(object)
(class)
ReplaceTruncatingArithmetic
firrtl.transforms.TopWiring
(case class)
TopWiringAnnotation
(case class)
TopWiringOutputFilesAnnotation
(class)
TopWiringTransform
firrtl.util
(trait)
BackendCompilationUtilities
logger
(trait)
LazyLogging
(object)
(class)
Logger
(object)
LogLevel
tutorial
tutorial.lesson1
(class)
AnalyzeCircuit
(class)
Ledger
tutorial.lesson2
(class)
AnalyzeCircuit
(class)
Ledger