RenameMap

final def !=(arg0: Any): Boolean

final def ##(): Int

def ++(renameMap: RenameMap): RenameMap

Create new RenameMap that merges this and renameMap

final def ==(arg0: Any): Boolean

def addMap(map: Map[Named, Seq[Named]]): Unit

def andThen(next: RenameMap): RenameMap

Chain a RenameMap with this RenameMap

def apply(t: CompleteTarget): Seq[CompleteTarget]

Renames a CompleteTarget

final def asInstanceOf[T0]: T0

val chained: Option[RenameMap]

def clone(): AnyRef

def copy(chained: Option[RenameMap] = chained): RenameMap

Creates a deep copy of this RenameMap

def delete(names: Seq[String]): Unit

Records that references in names are all deleted The reference's root module and circuit are determined by whomever called setModule or setCircuit last

def delete(name: String): Unit

Records named reference is deleted The reference's root module and circuit are determined by whomever called setModule or setCircuit last

def delete(name: ComponentName): Unit

def delete(name: ModuleName): Unit

def delete(name: CircuitName): Unit

def delete(name: CompleteTarget): Unit

Records that a CompleteTarget is deleted

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def get(key: Named): Option[Seq[Named]]

def get(key: ComponentName): Option[Seq[ComponentName]]

def get(key: ModuleName): Option[Seq[ModuleName]]

def get(key: CircuitName): Option[Seq[CircuitName]]

def get(key: IsMember): Option[Seq[IsMember]]

Get renames of a IsMember

def get(key: CircuitTarget): Option[Seq[CircuitTarget]]

Get renames of a CircuitTarget

def get(key: CompleteTarget): Option[Seq[CompleteTarget]]

Get renames of a CircuitTarget

final def getClass(): Class[_]

def getReverseRenameMap: RenameMap

def getUnderlying: Map[CompleteTarget, Seq[CompleteTarget]]

Returns the underlying map of rename information

def hasChanges: Boolean

def hashCode(): Int

final def isInstanceOf[T0]: Boolean

def keys: Iterator[CompleteTarget]

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

def record(from: IsMember, tos: Seq[IsMember]): Unit

Record that the from IsMember is renamed to another sequence of IsMembers

def record(from: IsMember, to: IsMember): Unit

Record that the from Member is renamed to another IsMember

def record(from: CircuitTarget, tos: Seq[CircuitTarget]): Unit

Record that the from CircuitTarget is renamed to another sequence of CircuitTargets

def record(from: CircuitTarget, to: CircuitTarget): Unit

Record that the from CircuitTarget is renamed to another CircuitTarget

def recordAll(map: Map[CompleteTarget, Seq[CompleteTarget]]): Unit

Records that the keys in map are also renamed to their corresponding value seqs.

def rename(from: String, tos: Seq[String]): Unit

Records how a reference maps to a new reference The reference's root module and circuit are determined by whomever called setModule or setCircuit last

def rename(from: String, to: String): Unit

Records how a reference maps to a new reference

def rename(from: ComponentName, tos: Seq[ComponentName]): Unit

def rename(from: ComponentName, to: ComponentName): Unit

def rename(from: Named, tos: Seq[Named]): Unit

def rename(from: Named, to: Named): Unit

def serialize: String

Serialize the underlying remapping of keys to new targets

def setCircuit(circuit: String): Unit

Sets mutable state to record current circuit we are visiting

def setModule(module: String): Unit

Sets mutable state to record current module we are visiting

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

val underlying: HashMap[CompleteTarget, Seq[CompleteTarget]]

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def finalize(): Unit