firrtl
Wraps modules or statements with their respective described nodes.
Wraps modules or statements with their respective described nodes. Descriptions come from DescriptionAnnotation.
Describing a module or any of its ports will turn it into a DescribedMod. Describing a Statement will turn it into
a (private) DescribedStmt.
should only be used by VerilogEmitter, described nodes will break other transforms.
Container of all annotations for a Firrtl compiler
This transforms "CHIRRTL", the chisel3 IR, to "Firrtl".
This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting circuit has only IR nodes, not WIR.
Current form of the Firrtl Circuit
Current form of the Firrtl Circuit
Form is a measure of addition restrictions on the legality of a Firrtl circuit. There is a notion of "highness" and "lowness" implemented in the compiler by extending scala.math.Ordered. "Lower" forms add additional restrictions compared to "higher" forms. This means that "higher" forms are strictly supersets of the "lower" forms. Thus, that any transform that operates on HighForm can also operate on MidForm or LowForm
Current State of the Circuit
Current State of the Circuit
The current state of the Firrtl AST
The current form of the circuit
The current collection of Annotation
A map of Named things that have been renamed. Generally only a return value from Transforms
Wraps exceptions from CustomTransforms so they can be reported appropriately
Traits for Annotations containing emitted components
Defines old API for Emission.
Defines old API for Emission. Deprecated
Exception indicating user error
Exception indicating user error
These exceptions indicate a problem due to bad input and thus do not include a stack trace. This can be extended by custom transform writers.
Emits input circuit Will replace Chirrtl constructs with Firrtl
Expands aggregate connects, removes dynamic accesses, and when statements.
Expands aggregate connects, removes dynamic accesses, and when statements. Checks for uninitialized values. Must accept a well-formed graph. Operates on working IR nodes.
Converts from the bare intermediate representation (ir.scala) to a working representation (WIR.scala)
Emits lowered input circuit
Runs a series of optimization passes on LowFirrtl
Runs a series of optimization passes on LowFirrtl
This is currently required for correct Verilog emission TODO Fix the above note
Emits middle Firrtl input circuit
Expands all aggregate types into many ground-typed components.
Expands all aggregate types into many ground-typed components. Must accept a well-formed graph of only middle Firrtl features. Operates on working IR nodes.
Runs runs only the optimization passes needed for Verilog emission
Emits Verilog without optimizations
Maintains a one to many graph of each modules instantiated child module.
Maintains a one to many graph of each modules instantiated child module. This graph can be searched for a path from a child module back to one of it's parents. If one is found a recursive loop has happened The graph is a map between the name of a node to set of names of that nodes children
Emits input circuit with no changes
Emits input circuit with no changes
Primarily useful for changing between .fir and .pb serialized formats
Firrtl output configuration specified by FirrtlExecutionOptions
Firrtl output configuration specified by FirrtlExecutionOptions
Derived from the fields of the execution options
Map old names to new names
Map old names to new names
Transforms that modify names should return a RenameMap with the CircuitState These are mutable datastructures for convenience
Resolves types, kinds, and flows, and checks the circuit legality.
Resolves types, kinds, and flows, and checks the circuit legality. Operates on working IR nodes and high Firrtl.
Extend for transforms that require resolved targets in their annotations Ensures all targets in annotations of a class in annotationClasses are resolved before the execute method
For transformations that are simply a sequence of transforms
Currently just an alias for the VerilogCompiler
The basic unit of operating on a Firrtl AST
Emits Verilog
Most of the chisel toolchain components require a topName which defines a circuit or a device under test.
Most of the chisel toolchain components require a topName which defines a circuit or a device under test. Much of the work that is done takes place in a directory. It would be simplest to require topName to be defined but in practice it is preferred to defer this. For example, in chisel, by deferring this it is possible for the execute there to first elaborate the circuit and then set the topName from that if it has not already been set.
(Since version 1.2) Use a FirrtlOptionsView, LoggerOptionsView, or construct your own view of an AnnotationSeq
Use this trait to define an options class that can add its private command line options to a externally declared parser.
Use this trait to define an options class that can add its private command line options to a externally declared parser. NOTE In all derived trait/classes, if you intend on maintaining backwards compatibility, be sure to add new options at the end of the current ones and don't remove any existing ones.
(Since version 1.2) Use firrtl.options.HasScoptOptions and/or library/transform registration
(Since version 1.2) Use new FirrtlStage infrastructure
(Since version 1.2) External users should use either FirrtlUserException or their own hierarchy
The firrtl compilation failed.
The firrtl compilation failed.
Some kind of hint as to what went wrong.
(Since version 1.2) Use FirrtlStage and examine the output AnnotationSeq directly
The options that firrtl supports in callable component sense
The options that firrtl supports in callable component sense
default is targetDir/topName.fir
default is targetDir/topName.v the .v is based on the compilerName parameter
which compiler to use
annotations to pass to compiler
(Since version 1.2) Use a FirrtlOptionsView or construct your own view of an AnnotationSeq
(Since version 1.2) Use FirrtlStage and examine the output AnnotationSeq directly
Indicates a successful execution of the firrtl compiler, returning the compiled result and the type of compile
Indicates a successful execution of the firrtl compiler, returning the compiled result and the type of compile
(Since version 1.2) Use FirrtlStage and examine the output AnnotationSeq directly
(Since version 1.2) Use Flow instead of Gender. This trait will be removed in 1.3
(Since version 1.2) Specify command line arguments in an Annotation mixing in HasScoptOptions
(Since version 1.2) Specify command line arguments in an Annotation mixing in HasScoptOptions
(Since version 1.2) Use firrtl.options.{ExecutionOptionsManager, TerminateOnExit, DuplicateHandling}
(Since version 1.2) Use firrtl.stage.TargetDirAnnotation
Chirrtl Form
Chirrtl Form
The form of the circuit emitted by Chisel. Not a true Firrtl form. Includes cmem, smem, and mport IR nodes which enable declaring memories separately form their ports. A "Higher" form than HighForm
See CDefMemory and CDefMPort
High Form
High Form
As detailed in the Firrtl specification https://github.com/ucb-bar/firrtl/blob/master/spec/spec.pdf
Also see firrtl.ir
Low Form
Low Form
The "lowest" form. In addition to the restrictions in MidForm:
Middle Form
Middle Form
A "lower" form than HighForm with the following restrictions:
Definitions and Utility functions for ir.PrimOps
Unknown Form
Unknown Form
Often passes may modify a circuit (e.g. InferTypes), but return a circuit in the same form it was given.
For this use case, use UnknownForm. It cannot be compared against other forms.
TODO(azidar): Replace with PreviousForm, which more explicitly encodes this requirement.
The stage package provides an implementation of the FIRRTL compiler using the firrtl.options package.
The stage package provides an implementation of the FIRRTL compiler using the firrtl.options package. This primarily consists of:
Given an expression, return an expression consisting of all sub-expressions concatenated (or flattened).
(Since version 1.2) Use DuplexFlow instead of BIGENDER. This case object will be removed in 1.3
The driver provides methods to access the firrtl compiler.
The driver provides methods to access the firrtl compiler. Invoke the compiler with either a FirrtlExecutionOption
(Since version 1.2) Use firrtl.stage.FirrtlStage
firrtl.Driver.execute(Array("--top-name Dummy --compiler verilog".split(" +"))
each approach has its own endearing aspects
val optionsManager = new ExecutionOptionsManager("firrtl") optionsManager.register( FirrtlExecutionOptionsKey -> new FirrtlExecutionOptions(topName = "Dummy", compilerName = "verilog")) firrtl.Driver.execute(optionsManager)
or a series of command line arguments
CompilerUtils.mergeTransforms to see how customTransformations are inserted
firrtlTests/DriverSpec.scala in the test directory for a lot more examples
(Since version 1.2) Use SinkFlow instead of FEMALE. This case object will be removed in 1.3
(Since version 1.2) External users should use either FirrtlUserException or their own hierarchy
(Since version 1.2) Use FirrtlStage and examine the output AnnotationSeq directly
(Since version 1.2) Use SourceFlow instead of MALE. This case object will be removed in 1.3
(Since version 1.2) Use firrtl.stage.TargetDirAnnotation
(Since version 1.2) Use UnknownFlow instead of UNKNOWNGENDER. This case object will be removed in 1.3
(Since version 1.2) Please migrate from 'Gender' to 'Flow'. This implicit conversion will be removed in 1.3