passes
Indicates that something should be inlined
Inline instances as indicated by existing InlineAnnotations
Inline instances as indicated by existing InlineAnnotations
Only use on legal Firrtl. Specifically, the restriction of instance loops must have been checked, or else this pass can infinitely recurse.
Pass is simple transform that is generally part of a larger Transform Has an UnknownForm, because larger Transform should specify form
Removes all firrtl.WSubAccess from circuit
Reports errors for any references that are not fully initialized
Reports errors for any references that are not fully initialized
Assumes single connection (ie. no last connect semantics)
,This pass looks for firrtl.WVoids left behind by ExpandWhens
Replaces FixedType with SIntType, and correctly aligns all binary points
Expand Whens
Expand Whens
This pass does the following things: $ - Remove last connect semantics $ - Remove conditional blocks $ - Eliminate concept of scoping $ - Consolidate attaches
Assumes all references are declared
,Assumes bulk connects and isInvalids have been expanded
Removes all aggregate types from a firrtl.ir.Circuit
Removes all aggregate types from a firrtl.ir.Circuit
wire foo : { a : UInt<32>, b : UInt<16> }lowers to
wire foo_a : UInt<32> wire foo_b : UInt<16>
Assumes firrtl.ir.Connects and firrtl.ir.IsInvalids only operate on firrtl.ir.Expressions of ground type
,Assumes firrtl.ir.SubAccesses have been removed
Remove ValidIf and replace IsInvalid with a connection to zero
Replaces constant firrtl.WSubAccess with firrtl.WSubIndex TODO Fold in to High Firrtl Const Prop
Resolve name collisions that would occur in LowerTypes
Resolve name collisions that would occur in LowerTypes
wire a = { b, c }[2]
wire a_0This lowers to:
wire a__0_b wire a__0_c wire a__1_b wire a__1_c wire a_0
There wouldn't be a collision even if we didn't map a -> a_, but there WOULD be collisions in references a[0] and a_0 so we still have to rename a
Must be run after InferTypes because ir.DefNodes need type
Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog
Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog
This pass finds every instance of (a % b) and: 1) adds a temporary node equal to (a % b) with width Max(W(a), W(b)) 2) replaces the reference to (a % b) with a bitslice of the temporary node to get back down to width Min(W(a), W(b))
This is technically incorrect firrtl, but allows the verilog emitter to emit correct verilog without needing to add temporary nodes
Makes changes to the Firrtl AST to make Verilog emission easier
Makes changes to the Firrtl AST to make Verilog emission easier
- For each instance, adds wires to connect to each port
The result of this pass is NOT legal Firrtl
Handles dynamic accesses to zero-length vectors.
Handles dynamic accesses to zero-length vectors.
Replaces "source" references to elements of zero-length vectors with always-invalid validif
,Removes attaches that become degenerate after zero-length-accessor removal
,Removes signals resulting from accesses to a zero-length vector from attach groups
,Removes assignments that use a zero-length vector as a sink
Given a mask, return a bitmask corresponding to the desired datatype.
Given a mask, return a bitmask corresponding to the desired datatype. Requirements:
wire mask: {x: UInt<1>, y: UInt<1>}
wire data: {x: UInt<2>, y: SInt<2>}
// this would return:
cat(cat(mask.x, mask.x), cat(mask.y, mask.y))
(Since version 1.2) Use 'CheckFlows'. This object will be removed in 1.3
(Since version 1.2) Use 'ResolveFlows'. This will be removed in 1.3
(Since version 1.2) Use transforms.VerilogRename, will be removed in 1.3