This class performs the primary work of the transform: splitting readwrite ports into separate read and write ports while simultaneously compiling memory latencies to combinational-read memories with delay pipelines.
This class performs the primary work of the transform: splitting readwrite ports into separate read and write ports while simultaneously compiling memory latencies to combinational-read memories with delay pipelines. It is represented as a class that takes a module as a constructor argument, as it encapsulates the mutable state required to analyze and transform one module.
The final transformed module is found in the (sole public) field transformed
A component, e.g.
A component, e.g. register etc. Must be declared only once under the TopAnnotation
Annotates the name of the pins to add for WiringTransform
Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file.
Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file. This will not generate wmask ports if not needed. Creates the minimum # of black boxes needed by the design.
Resolves annotation ref to memories that exactly match (except name) another memory
Changes memory port names to standard port names (i.e.
Changes memory port names to standard port names (i.e. RW0 instead T_408)
Determines if a write mask is needed (wmode/en and wmask are equivalent).
Determines if a write mask is needed (wmode/en and wmask are equivalent). Populates the maskGran field of DefAnnotatedMemory Annotations:
Annotates sequential memories that are candidates for macro replacement.
Annotates sequential memories that are candidates for macro replacement. Requirements for macro replacement:
(Since version 1.2.1) Internal helper objects from VerilogMemDelays will be removed in 1.3