RenameAnnotatedMemoryPorts

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

final def asInstanceOf[T0]: T0

def clone(): AnyRef

def createMemProto(m: DefAnnotatedMemory): DefAnnotatedMemory

Renames memory ports to a standard naming scheme:

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def execute(state: CircuitState): CircuitState

Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.

final def getClass(): Class[_]

def getMemPortMap(m: DefAnnotatedMemory, memPortMap: MemPortMap): Unit

Maps the serialized form of all memory port field names to the corresponding new memory port field Expression.

def hashCode(): Int

def inputForm: CircuitForm

The firrtl.CircuitForm that this transform requires to operate on

final def isInstanceOf[T0]: Boolean

val logger: Logger

def name: String

A convenience function useful for debugging and error messages

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

def outputForm: CircuitForm

The firrtl.CircuitForm that this transform outputs

def run(c: Circuit): Circuit

final def runTransform(state: CircuitState): CircuitState

Perform the transform and update annotations.

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

def transform(state: CircuitState): CircuitState

A mathematical transform on some type

def updateMemMods(m: DefModule): DefModule

Replaces candidate memories and their references with standard port names

def updateMemStmts(memPortMap: MemPortMap)(s: Statement): Statement

Replaces candidate memories with memories with standard port names Does not update the references (this is done via updateStmtRefs)

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def finalize(): Unit

final def getMyAnnotations(state: CircuitState): Seq[Annotation]

Convenience method to get annotations relevant to this Transform