transforms

Type Members

1. sealed trait BlackBoxHelperAnno extends Annotation

   

2. case class BlackBoxInlineAnno(target: ModuleName, name: String, text: String) extends BlackBoxHelperAnno with SingleTargetAnnotation[ModuleName] with Product with Serializable

   

3. class BlackBoxNotFoundException extends FirrtlUserException

   

   Exception indicating that a blackbox wasn't found

4. case class BlackBoxPathAnno(target: ModuleName, path: String) extends BlackBoxHelperAnno with SingleTargetAnnotation[ModuleName] with Product with Serializable

   

5. case class BlackBoxResourceAnno(target: ModuleName, resourceId: String) extends BlackBoxHelperAnno with SingleTargetAnnotation[ModuleName] with Product with Serializable

   

6. case class BlackBoxResourceFileNameAnno(resourceFileName: String) extends BlackBoxHelperAnno with NoTargetAnnotation with Product with Serializable

   

7. class BlackBoxSourceHelper extends Transform

   

   Handle source for Verilog ExtModules (BlackBoxes)

   Handle source for Verilog ExtModules (BlackBoxes)

   This transform handles the moving of Verilog source for black boxes into the target directory so that it can be accessed by verilator or other backend compilers While parsing it's annotations it looks for a BlackBoxTargetDir annotation that will set the directory where the Verilog will be written. This annotation is typically be set by the execution harness, or directly in the tests

8. case class BlackBoxTargetDirAnno(targetDir: String) extends BlackBoxHelperAnno with NoTargetAnnotation with Product with Serializable

   

9. class CheckCombLoops extends Transform with RegisteredTransform

   

   Finds and detects combinational logic loops in a circuit, if any exist.

   Finds and detects combinational logic loops in a circuit, if any exist. Returns the input circuit with no modifications.

   Exceptions thrown

   firrtl.transforms.CheckCombLoops.CombLoopException if a loop is found

   Note

   The pass will throw exceptions on "false paths"

   ,

   The pass relies on ExtModulePathAnnotations to find loops through ExtModules

   ,

   The pass looks for loops through combinational-read memories

   ,

   Output form: Low FIRRTL (identity transform)

   ,

   Input form: Low FIRRTL

10. case class CombinationalPath(sink: ReferenceTarget, sources: Seq[ReferenceTarget]) extends Annotation with Product with Serializable

    

11. class CombineCats extends Transform

    

    Combine Cat DoPrims

    Combine Cat DoPrims

    Expands the arguments of any Cat DoPrims if they are references to other Cat DoPrims. Operates only on Cat DoPrims that are node values.

    Use MaxCatLenAnnotation to limit the number of elements that can be concatenated. The default maximum number of elements is 10.

12. class ConstantPropagation extends Transform with ResolvedAnnotationPaths

    

13. class DeadCodeElimination extends Transform with ResolvedAnnotationPaths with RegisteredTransform

    

    Dead Code Elimination (DCE)

    Dead Code Elimination (DCE)

    Performs DCE by constructing a global dependency graph starting with top-level outputs, external module ports, and simulation constructs as circuit sinks. External modules can optionally be eligible for DCE via the OptimizableExtModuleAnnotation.

    Dead code is eliminated across module boundaries. Wires, ports, registers, and memories are all eligible for removal. Components marked with a DontTouchAnnotation will be treated as a circuit sink and thus anything that drives such a marked component will NOT be removed.

    This transform preserves deduplication. All instances of a given firrtl.ir.DefModule are treated as the same individual module. Thus, while certain instances may have dead code due to the circumstances of their instantiation in their parent module, they will still not be removed. To remove such modules, use the NoDedupAnnotation to prevent deduplication.

14. class DedupModules extends Transform

    

    Only use on legal Firrtl.

    Only use on legal Firrtl.

    Specifically, the restriction of instance loops must have been checked, or else this pass can infinitely recurse

15. case class DontTouchAnnotation(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] with Product with Serializable

    

    A component that should be preserved

    A component that should be preserved

    DCE treats the component as a top-level sink of the circuit

16. case class ExtModulePathAnnotation(source: ReferenceTarget, sink: ReferenceTarget) extends Annotation with Product with Serializable

    

17. class FixAddingNegativeLiterals extends Transform

    

    Replaces adding a negative literal with subtracting that literal

    Replaces adding a negative literal with subtracting that literal

    Verilator has a lint warning if a literal is negated in an expression, because it adds a bit to the literal and thus not all expressions in the add are the same. This is fixed here when we directly subtract the literal instead.

18. class Flatten extends Transform

    

    Takes flatten annotations for module instances and modules and inline the entire hierarchy of modules down from the annotations.

    Takes flatten annotations for module instances and modules and inline the entire hierarchy of modules down from the annotations. This transformation instantiates and is based on the InlineInstances transformation.

    Note

    Instances of extmodules are not (and cannot be) inlined

    ,

    Flattening a module means inlining all its fully-defined child instances

19. case class FlattenAnnotation(target: Named) extends SingleTargetAnnotation[Named] with Product with Serializable

    

    Tags an annotation to be consumed by this transform

20. class FlattenRegUpdate extends Transform

    

    Flatten register update

    Flatten register update

    This transform flattens register updates into a single expression on the rhs of connection to the register

21. class GroupAndDedup extends Transform

    

    Splits a module into multiple modules by grouping its components via GroupAnnotation's Tries to deduplicate the resulting circuit

22. case class GroupAnnotation(components: Seq[ComponentName], newModule: String, newInstance: String, outputSuffix: Option[String] = None, inputSuffix: Option[String] = None) extends Annotation with Product with Serializable

    

    Specifies a group of components, within a module, to pull out into their own module Components that are only connected to a group's components will also be included

    Specifies a group of components, within a module, to pull out into their own module Components that are only connected to a group's components will also be included

    components

    components in this group

    newModule

    suggested name of the new module

    newInstance

    suggested name of the instance of the new module

    outputSuffix

    suggested suffix of any output ports of the new module

    inputSuffix

    suggested suffix of any input ports of the new module

23. class GroupComponents extends Transform

    

    Splits a module into multiple modules by grouping its components via GroupAnnotation's

24. class IdentityTransform extends Transform

    

    Transform that applies an identity function.

    Transform that applies an identity function. This returns an unmodified CircuitState.

25. class InferResets extends Transform

    

    Infers the concrete type of ResetTypes by their connections

    Infers the concrete type of ResetTypes by their connections

    There are 3 cases 1. An abstract reset driven by and/or driving only asynchronous resets will be inferred as asynchronous reset 1. An abstract reset driven by and/or driving both asynchronous and synchronous resets will error 1. Otherwise, the reset is inferred as synchronous (i.e. the abstract reset is only invalidated or is driven by or drives only synchronous resets)

    Note

    This transform should be run before DedupModules so that similar Modules from generator languages like Chisel can infer differently

    ,

    This is a global inference because ports can be of type ResetType

26. class InlineBitExtractionsTransform extends Transform

    

    Inline nodes that are simple bits

27. class InlineCastsTransform extends Transform

    

    Inline nodes that are simple casts

28. class InlineNotsTransform extends Transform

    

    Inline nodes that are simple nots

29. class LegalizeAndReductionsTransform extends Transform

    

    Turns andr for expression > 64-bit into equality check with all ones

    Turns andr for expression > 64-bit into equality check with all ones

    Workaround a bug in Verilator v4.026 - v4.032 (inclusive). For context, see https://github.com/verilator/verilator/issues/2300

30. class LegalizeClocksTransform extends Transform

    

    Ensure Clocks to be emitted are legal Verilog

31. case class LogicNode(name: String, inst: Option[String] = None, memport: Option[String] = None) extends Product with Serializable

    

    A case class that represents a net in the circuit.

    A case class that represents a net in the circuit. This is necessary since combinational loop checking is an analysis on the netlist of the circuit; the fields are specialized for low FIRRTL. Since all wires are ground types, a given ground type net may only be a subfield of an instance or a memory port. Therefore, it is uniquely specified within its module context by its name, its optional parent instance (a WDefInstance or WDefMemory), and its optional memory port name.

32. case class MaxCatLenAnnotation(maxCatLen: Int) extends NoTargetAnnotation with Product with Serializable

    

33. case class NoDedupAnnotation(target: ModuleName) extends SingleTargetAnnotation[ModuleName] with Product with Serializable

    

    A component, e.g.

    A component, e.g. register etc. Must be declared only once under the TopAnnotation

34. case class OptimizableExtModuleAnnotation(target: ModuleName) extends SingleTargetAnnotation[ModuleName] with Product with Serializable

    

    An firrtl.ir.ExtModule that can be optimized

    An firrtl.ir.ExtModule that can be optimized

    Firrtl does not know the semantics of an external module. This annotation provides some "greybox" information that the external module does not have any side effects. In particular, this means that the external module can be Dead Code Eliminated.

    Note

    Unlike DontTouchAnnotation, we don't care if the annotation is deleted

35. class RemoveKeywordCollisions extends Transform

    

    Transform that removes collisions with reserved keywords

36. class RemoveReset extends Transform

    

    Remove Synchronous Reset

    Remove Synchronous Reset

    Note

    This pass must run after LowerTypes

37. class RemoveWires extends Transform

    

    Replace wires with nodes in a legal, flow-forward order

    Replace wires with nodes in a legal, flow-forward order

    This pass must run after LowerTypes because Aggregate-type wires have multiple connections that may be impossible to order in a flow-foward way

38. class RenameModules extends Transform

    

    Rename Modules

    Rename Modules

    using namespace created by analyses.GetNamespace, create unique names for modules

39. class ReplaceTruncatingArithmetic extends Transform

    

    Replaces non-expanding arithmetic

    Replaces non-expanding arithmetic

    In the case where the result of add or sub immediately throws away the expanded msb, this transform will replace the operation with a non-expanding operator addw or subw respectively.

    Note

    This replaces some FIRRTL primops with ops that are not actually legal FIRRTL. They are useful for emission to languages that support non-expanding arithmetic (like Verilog)

40. class SimplifyMems extends Transform

    

    Lowers memories without splitting them, but without the complexity of ReplaceMemMacros

41. class VerilogRename extends RemoveKeywordCollisions

    

    Transform that removes collisions with Verilog keywords