SystemVerilogEmitter
Related Doc:
package firrtl
Used by getRenderer, it has machinery to produce verilog from IR.
Used by getRenderer, it has machinery to produce verilog from IR. Making this a class allows access to particular parts of the verilog emission.
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
Input Firrtl AST
A transformed Firrtl AST
Gets a reference to a verilog renderer.
Gets a reference to a verilog renderer. This is used by the current standard verilog emission process but allows access to individual portions, in particular, this function can be used to generate the header for a verilog file without generating anything else.
comments to be emitted
the start module
a way of finding other modules
where rendering will be placed
the render reference
Gets a reference to a verilog renderer.
Gets a reference to a verilog renderer. This is used by the current standard verilog emission process but allows access to individual portions, in particular, this function can be used to generate the header for a verilog file without generating anything else.
the start module
a way of finding other modules
where rendering will be placed
the render reference
The firrtl.CircuitForm that this transform requires to operate on
The firrtl.CircuitForm that this transform requires to operate on
A convenience function useful for debugging and error messages
A convenience function useful for debugging and error messages
The firrtl.CircuitForm that this transform outputs
The firrtl.CircuitForm that this transform outputs
An output suffix to use if the output of this Emitter was written to a file
An output suffix to use if the output of this Emitter was written to a file
Perform the transform and update annotations.
Perform the transform and update annotations.
Input Firrtl AST
A transformed Firrtl AST
Turn Params into Verilog Strings
Turn Params into Verilog Strings
A mathematical transform on some type
A mathematical transform on some type
an output object of the same type
Preamble for every emitted Verilog file
Preamble for every emitted Verilog file
(Since version ) see corresponding Javadoc for more information.
Convenience method to get annotations relevant to this Transform
Convenience method to get annotations relevant to this Transform
The CircuitState form which to extract annotations
A collection of annotations
(Since version 1.1) Just collect the actual Annotation types the transform wants