BackendCompilationUtilities
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package util
Parent directory for tests
Copy the contents of a resource to a destination file.
Copy the contents of a resource to a destination file.
the name of the resource
the file to write it into
Create a test directory
Create a test directory
Will create outer directory called testName then inner directory based on the current time
compule chirrtl to verilog by using a separate process
compule chirrtl to verilog by using a separate process
basename of the file
directory where file lives
true if compiler completed successfully
Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.
Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.
The Verilator prefix will be V$dutFile, and running this will generate C++ sources and headers as well as a makefile to compile them.
Verilator will automatically locate the top-level module as the one among all the files which are not included elsewhere. If multiple ones exist, the compilation will fail.
If the file BlackBoxSourceHelper.fileListName (or an overridden .f resource filename that is specified with the optional resourceFileName parameter) exists in the output directory, it contains a list of source files to be included. Filter out any files in the vSources sequence that are in this file so we don't include the same file multiple times. This complication is an attempt to work-around the fact that clients used to have to explicitly include additional Verilog sources. Now, more of that is automatic.
name of the DUT .v without the .v extension
output directory
list of additional Verilog sources to compile
C++ testharness to compile/link against
specifies if VCD tracing should be suppressed
specifies what filename to look for to find a .f file
Creates and runs a Yosys script that creates and runs SAT on a miter circuit.
Creates and runs a Yosys script that creates and runs SAT on a miter circuit. Returns false if SAT succeeds, true otherwise
The custom and reference Verilog files must not contain any modules with the same name otherwise Yosys will not be able to create a miter circuit
name of the DUT with custom transforms without the .v extension
name of the DUT without custom transforms without the .v extension
directory containing verilog files
signals to set for SAT, format is (timestep, signal, value)
Creates and runs a Yosys script that creates and runs SAT on a miter circuit.
Creates and runs a Yosys script that creates and runs SAT on a miter circuit. Returns true if SAT succeeds, false otherwise
The custom and reference Verilog files must not contain any modules with the same name otherwise Yosys will not be able to create a miter circuit
name of the DUT with custom transforms without the .v extension
name of the DUT without custom transforms without the .v extension
directory containing verilog files
signals to set for SAT, format is (timestep, signal, value)