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p

firrtl

package firrtl

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Type Members

  1. case class AnnotationMap (annotations: Seq[Annotation]) extends Product with Serializable

    Container of all annotations for a Firrtl compiler.

  2. case class CDefMPort (info: Info, name: String, tpe: Type, mem: String, exps: Seq[Expression], direction: MPortDir) extends Statement with Product with Serializable
  3. case class CDefMemory (info: Info, name: String, tpe: Type, size: Int, seq: Boolean) extends Statement with Product with Serializable
  4. class ChirrtlToHighFirrtl extends CoreTransform

    This transforms "CHIRRTL", the chisel3 IR, to "Firrtl".

    This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting circuit has only IR nodes, not WIR.

  5. sealed abstract class CircuitForm extends Ordered[CircuitForm]

    Current form of the Firrtl Circuit

    Current form of the Firrtl Circuit

    Form is a measure of addition restrictions on the legality of a Firrtl circuit. There is a notion of "highness" and "lowness" implemented in the compiler by extending scala.math.Ordered. "Lower" forms add additional restrictions compared to "higher" forms. This means that "higher" forms are strictly supersets of the "lower" forms. Thus, that any transform that operates on HighForm can also operate on MidForm or LowForm

  6. case class CircuitState (circuit: Circuit, form: CircuitForm, annotations: Option[AnnotationMap] = None, renames: Option[RenameMap] = None) extends Product with Serializable

    Current State of the Circuit

    Current State of the Circuit

    circuit

    The current state of the Firrtl AST

    form

    The current form of the circuit

    annotations

    The current collection of Annotation

    renames

    A map of Named things that have been renamed. Generally only a return value from Transforms

  7. case class CommonOptions (topName: String = "", targetDirName: String = ".", globalLogLevel: logger.LogLevel.Value = LogLevel.None, logToFile: Boolean = false, logClassNames: Boolean = false, classLogLevels: Map[String, logger.LogLevel.Value] = Map.empty) extends ComposableOptions with Product with Serializable

    Most of the chisel toolchain components require a topName which defines a circuit or a device under test.

    Most of the chisel toolchain components require a topName which defines a circuit or a device under test. Much of the work that is done takes place in a directory. It would be simplest to require topName to be defined but in practice it is preferred to defer this. For example, in chisel, by deferring this it is possible for the execute there to first elaborate the circuit and then set the topName from that if it has not already been set.

  8. trait Compiler extends LazyLogging
  9. trait ComposableOptions extends AnyRef

    Use this trait to define an options class that can add its private command line options to a externally declared parser

  10. trait Constraint extends AnyRef
  11. sealed abstract class CoreTransform extends SeqTransform
  12. sealed abstract class EmitAnnotation extends AnyRef
  13. sealed abstract class EmittedAnnotation [T <: EmittedComponent] extends AnyRef

    Super class for Annotations containing emitted components

    Super class for Annotations containing emitted components

    Note

    These annotations cannot be serialized and deserialized to/from an annotation file

  14. sealed abstract class EmittedCircuit extends EmittedComponent
  15. sealed abstract class EmittedComponent extends AnyRef
  16. final case class EmittedFirrtlCircuit (name: String, value: String) extends EmittedCircuit with Product with Serializable
  17. final case class EmittedFirrtlModule (name: String, value: String) extends EmittedModule with Product with Serializable
  18. sealed abstract class EmittedModule extends EmittedComponent
  19. final case class EmittedVerilogCircuit (name: String, value: String) extends EmittedCircuit with Product with Serializable
  20. final case class EmittedVerilogModule (name: String, value: String) extends EmittedModule with Product with Serializable
  21. trait Emitter extends Transform

    Defines old API for Emission.

    Defines old API for Emission. Deprecated

  22. case class EmitterException (message: String) extends PassException with Product with Serializable
  23. class ExecutionOptionsManager extends HasParser with HasCommonOptions

  24. case class ExpWidth (arg1: Width) extends Width with HasMapWidth with Product with Serializable
  25. class FIRRTLException extends Exception
  26. sealed abstract class FirrtlEmitter extends Transform with Emitter
  27. case class FirrtlExecutionFailure (message: String) extends FirrtlExecutionResult with Product with Serializable

    The firrtl compilation failed.

    The firrtl compilation failed.

    message

    Some kind of hint as to what went wrong.

  28. case class FirrtlExecutionOptions (inputFileNameOverride: String = "", outputFileNameOverride: String = "", compilerName: String = "verilog", infoModeName: String = "append", inferRW: Seq[String] = Seq.empty, firrtlSource: Option[String] = None, customTransforms: Seq[Transform] = List.empty, annotations: List[Annotation] = List.empty, annotationFileNameOverride: String = "", outputAnnotationFileName: String = "", forceAppendAnnoFile: Boolean = false, emitOneFilePerModule: Boolean = false, dontCheckCombLoops: Boolean = false, noDCE: Boolean = false) extends ComposableOptions with Product with Serializable

    The options that firrtl supports in callable component sense

    The options that firrtl supports in callable component sense

    inputFileNameOverride

    default is targetDir/topName.fir

    outputFileNameOverride

    default is targetDir/topName.v the .v is based on the compilerName parameter

    compilerName

    which compiler to use

    annotations

    annotations to pass to compiler

  29. sealed trait FirrtlExecutionResult extends AnyRef
  30. case class FirrtlExecutionSuccess (emitType: String, emitted: String) extends FirrtlExecutionResult with Product with Serializable

    Indicates a successful execution of the firrtl compiler, returning the compiled result and the type of compile

    Indicates a successful execution of the firrtl compiler, returning the compiled result and the type of compile

    emitType

    The name of the compiler used, currently "high", "middle", "low", or "verilog"

    emitted

    The emitted result of compilation

  31. trait Gender extends AnyRef
  32. trait HasCommonOptions extends AnyRef
  33. trait HasFirrtlOptions extends AnyRef
  34. abstract class HasParser extends AnyRef
  35. class HighFirrtlCompiler extends Compiler

    Emits input circuit Will replace Chirrtl constructs with Firrtl

  36. class HighFirrtlEmitter extends FirrtlEmitter
  37. class HighFirrtlToMiddleFirrtl extends CoreTransform

    Expands aggregate connects, removes dynamic accesses, and when statements.

    Expands aggregate connects, removes dynamic accesses, and when statements. Checks for uninitialized values. Must accept a well-formed graph. Operates on working IR nodes.

  38. class IRToWorkingIR extends CoreTransform

    Converts from the bare intermediate representation (ir.scala) to a working representation (WIR.scala)

  39. case class InvalidEscapeCharException (message: String) extends ParserException with Product with Serializable
  40. case class InvalidStringLitException (message: String) extends ParserException with Product with Serializable
  41. trait Kind extends AnyRef
  42. abstract class LexerHelper extends AnyRef
  43. class LowFirrtlCompiler extends Compiler

    Emits lowered input circuit

  44. class LowFirrtlEmitter extends FirrtlEmitter
  45. class LowFirrtlOptimization extends CoreTransform

    Runs a series of optimization passes on LowFirrtl

    Runs a series of optimization passes on LowFirrtl

    Note

    This is currently required for correct Verilog emission TODO Fix the above note

  46. abstract class MPortDir extends FirrtlNode
  47. case class MaxWidth (args: Seq[Width]) extends Width with HasMapWidth with Product with Serializable
  48. class MemoizedHash [T] extends AnyRef
  49. class MiddleFirrtlCompiler extends Compiler

    Emits middle Firrtl input circuit

  50. class MiddleFirrtlEmitter extends FirrtlEmitter
  51. class MiddleFirrtlToLowFirrtl extends CoreTransform

    Expands all aggregate types into many ground-typed components.

    Expands all aggregate types into many ground-typed components. Must accept a well-formed graph of only middle Firrtl features. Operates on working IR nodes.

  52. case class MinWidth (args: Seq[Width]) extends Width with HasMapWidth with Product with Serializable
  53. case class MinusWidth (arg1: Width, arg2: Width) extends Width with HasMapWidth with Product with Serializable
  54. class ModuleGraph extends AnyRef

    Maintains a one to many graph of each modules instantiated child module.

    Maintains a one to many graph of each modules instantiated child module. This graph can be searched for a path from a child module back to one of it's parents. If one is found a recursive loop has happened The graph is a map between the name of a node to set of names of that nodes children

  55. class Namespace extends AnyRef
  56. final case class OneFilePerModule (targetDir: String) extends OutputConfig with Product with Serializable
  57. sealed abstract class OutputConfig extends AnyRef

    Firrtl output configuration specified by FirrtlExecutionOptions

    Firrtl output configuration specified by FirrtlExecutionOptions

    Derived from the fields of the execution options

    See also

    FirrtlExecutionOptions.getOutputConfig

  58. case class ParameterNotSpecifiedException (message: String) extends ParserException with Product with Serializable
  59. case class ParameterRedefinedException (message: String) extends ParserException with Product with Serializable
  60. class ParserException extends Exception
  61. case class PlusWidth (arg1: Width, arg2: Width) extends Width with HasMapWidth with Product with Serializable
  62. class RenameMap extends AnyRef
  63. class ResolveAndCheck extends CoreTransform

    Resolves types, kinds, and genders, and checks the circuit legality.

    Resolves types, kinds, and genders, and checks the circuit legality. Operates on working IR nodes and high Firrtl.

  64. abstract class SeqTransform extends Transform with SeqTransformBased

    For transformations that are simply a sequence of transforms

  65. trait SeqTransformBased extends AnyRef
  66. final case class SingleFile (targetFile: String) extends OutputConfig with Product with Serializable
  67. trait StringLitHandler extends AnyRef
  68. abstract class Transform extends LazyLogging

    The basic unit of operating on a Firrtl AST

  69. case class VRandom (width: BigInt) extends Expression with Product with Serializable
  70. case class VarWidth (name: String) extends Width with HasMapWidth with Product with Serializable
  71. class VerilogCompiler extends Compiler

    Emits Verilog

  72. class VerilogEmitter extends SeqTransform with Emitter
  73. class Visitor extends FIRRTLBaseVisitor[FirrtlNode]
  74. case class WDefInstance (info: Info, name: String, module: String, tpe: Type) extends Statement with IsDeclaration with Product with Serializable
  75. case class WDefInstanceConnector (info: Info, name: String, module: String, tpe: Type, portCons: Seq[(Expression, Expression)]) extends Statement with IsDeclaration with Product with Serializable
  76. class WGeq extends Constraint
  77. case class WRef (name: String, tpe: Type, kind: Kind, gender: Gender) extends Expression with Product with Serializable
  78. case class WSubAccess (expr: Expression, index: Expression, tpe: Type, gender: Gender) extends Expression with Product with Serializable
  79. case class WSubField (expr: Expression, name: String, tpe: Type, gender: Gender) extends Expression with Product with Serializable
  80. case class WSubIndex (expr: Expression, value: Int, tpe: Type, gender: Gender) extends Expression with Product with Serializable
  81. class WrappedExpression extends AnyRef
  82. class WrappedType extends AnyRef
  83. class WrappedWidth extends AnyRef

Value Members

  1. object Addw extends PrimOp with Product with Serializable
  2. object BIGENDER extends Gender with Product with Serializable
  3. object ChirrtlForm extends CircuitForm with Product with Serializable

    Chirrtl Form

    Chirrtl Form

    The form of the circuit emitted by Chisel. Not a true Firrtl form. Includes cmem, smem, and mport IR nodes which enable declaring memories separately form their ports. A "Higher" form than HighForm

    See CDefMemory and CDefMPort

  4. object CompilerUtils extends LazyLogging
  5. object Driver

    The driver provides methods to access the firrtl compiler.

    The driver provides methods to access the firrtl compiler. Invoke the compiler with either a FirrtlExecutionOption

    Examples: 

    1. firrtl.Driver.execute(Array("--top-name Dummy --compiler verilog".split(" +"))

      each approach has its own endearing aspects

      2. , 

    2. val optionsManager = new ExecutionOptionsManager("firrtl")
optionsManager.register(
    FirrtlExecutionOptionsKey ->
    new FirrtlExecutionOptions(topName = "Dummy", compilerName = "verilog"))
firrtl.Driver.execute(optionsManager)

      or a series of command line arguments

    See also

    CompilerUtils.mergeTransforms to see how customTransformations are inserted

    firrtlTests/DriverSpec.scala in the test directory for a lot more examples

  6. object Dshlw extends PrimOp with Product with Serializable
  7. object EmitAllModulesAnnotation extends EmitAnnotation
  8. object EmitCircuitAnnotation extends EmitAnnotation
  9. object EmittedCircuitAnnotation
  10. object EmittedFirrtlCircuitAnnotation extends EmittedAnnotation[EmittedFirrtlCircuit]
  11. object EmittedFirrtlModuleAnnotation extends EmittedAnnotation[EmittedFirrtlModule]
  12. object EmittedModuleAnnotation
  13. object EmittedVerilogCircuitAnnotation extends EmittedAnnotation[EmittedVerilogCircuit]
  14. object EmittedVerilogModuleAnnotation extends EmittedAnnotation[EmittedVerilogModule]
  15. object EmptyExpression extends Expression with Product with Serializable
  16. object ExpKind extends Kind with Product with Serializable
  17. object FEMALE extends Gender with Product with Serializable
  18. object FIRRTLStringLitHandler extends StringLitHandler
  19. object FileUtils
  20. object HighForm extends CircuitForm with Product with Serializable

    High Form

    High Form

    As detailed in the Firrtl specification https://github.com/ucb-bar/firrtl/blob/master/spec/spec.pdf

    Also see firrtl.ir

  21. object InstanceKind extends Kind with Product with Serializable
  22. object LowForm extends CircuitForm with Product with Serializable

    Low Form

    Low Form

    The "lowest" form. In addition to the restrictions in MidForm:

    • All aggregate types (vector/bundle) must have been removed
    • All implicit truncations must be made explicit
  23. object MALE extends Gender with Product with Serializable
  24. object MInfer extends MPortDir with Product with Serializable
  25. object MRead extends MPortDir with Product with Serializable
  26. object MReadWrite extends MPortDir with Product with Serializable
  27. object MWrite extends MPortDir with Product with Serializable
  28. object Mappers
  29. object MemKind extends Kind with Product with Serializable
  30. object MemoizedHash
  31. object MidForm extends CircuitForm with Product with Serializable

    Middle Form

    Middle Form

    A "lower" form than HighForm with the following restrictions:

    • All widths must be explicit
    • All whens must be removed
    • There can only be a single connection to any element
  32. object Namespace
  33. object NodeKind extends Kind with Product with Serializable
  34. object Parser extends LazyLogging
  35. object PoisonKind extends Kind with Product with Serializable
  36. object PortKind extends Kind with Product with Serializable
  37. object PrimOps extends LazyLogging

    Definitions and Utility functions for ir.PrimOps

  38. object RegKind extends Kind with Product with Serializable
  39. object RenameMap

    RenameMap maps old names to modified names.

    RenameMap maps old names to modified names. Generated by transformations that modify names

  40. object Shlw extends PrimOp with Product with Serializable
  41. object Subw extends PrimOp with Product with Serializable
  42. object TargetDirAnnotation extends GlobalCircuitAnnotation

    annotations.GlobalCircuitAnnotation that contains the CommonOptions target directory

  43. object UNKNOWNGENDER extends Gender with Product with Serializable
  44. object UnknownForm extends CircuitForm with Product with Serializable

    Unknown Form

    Unknown Form

    Often passes may modify a circuit (e.g. InferTypes), but return a circuit in the same form it was given.

    For this use case, use UnknownForm. It cannot be compared against other forms.

    TODO(azidar): Replace with PreviousForm, which more explicitly encodes this requirement.

  45. object Utils extends LazyLogging
  46. object VerilogStringLitHandler extends StringLitHandler
  47. object WDefInstance extends Serializable
  48. object WGeq
  49. object WInvalid extends Expression with Product with Serializable
  50. object WRef extends Serializable
  51. object WSubField extends Serializable
  52. object WVoid extends Expression with Product with Serializable
  53. object WireKind extends Kind with Product with Serializable
  54. object WrappedExpression
  55. object WrappedType
  56. object WrappedWidth
  57. object bitWidth
  58. object castRhs
  59. object connectFields
  60. object flattenType
  61. object fromBits
  62. object getWidth
  63. object seqCat
  64. object toBits

    Given an expression, return an expression consisting of all sub-expressions concatenated (or flattened).

Ungrouped